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+microblaze_run_OBJECTS = $(am_microblaze_run_OBJECTS)
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(am__DEPENDENCIES_1)
+am_mips_run_OBJECTS =
+mips_run_OBJECTS = $(am_mips_run_OBJECTS)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_run_DEPENDENCIES = mips/nrun.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/libsim.a $(am__DEPENDENCIES_1)
+am_mn10300_run_OBJECTS =
+mn10300_run_OBJECTS = $(am_mn10300_run_OBJECTS)
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o mn10300/libsim.a \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(am__DEPENDENCIES_1)
+am_moxie_run_OBJECTS =
+moxie_run_OBJECTS = $(am_moxie_run_OBJECTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_DEPENDENCIES = moxie/nrun.o \
+@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/libsim.a \
+@SIM_ENABLE_ARCH_moxie_TRUE@ $(am__DEPENDENCIES_1)
+am_msp430_run_OBJECTS =
+msp430_run_OBJECTS = $(am_msp430_run_OBJECTS)
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_DEPENDENCIES = msp430/nrun.o \
+@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/libsim.a \
+@SIM_ENABLE_ARCH_msp430_TRUE@ $(am__DEPENDENCIES_1)
+am_or1k_run_OBJECTS =
+or1k_run_OBJECTS = $(am_or1k_run_OBJECTS)
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_DEPENDENCIES = or1k/nrun.o \
+@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/libsim.a $(am__DEPENDENCIES_1)
+ppc_psim_SOURCES = ppc/psim.c
+ppc_psim_OBJECTS = ppc/psim.$(OBJEXT)
+ppc_psim_LDADD = $(LDADD)
+am_ppc_run_OBJECTS =
+ppc_run_OBJECTS = $(am_ppc_run_OBJECTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_DEPENDENCIES = ppc/main.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a $(am__DEPENDENCIES_1)
+am_pru_run_OBJECTS =
+pru_run_OBJECTS = $(am_pru_run_OBJECTS)
+@SIM_ENABLE_ARCH_pru_TRUE@pru_run_DEPENDENCIES = pru/nrun.o \
+@SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a $(am__DEPENDENCIES_1)
+am_riscv_run_OBJECTS =
+riscv_run_OBJECTS = $(am_riscv_run_OBJECTS)
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_DEPENDENCIES = riscv/nrun.o \
+@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/libsim.a \
+@SIM_ENABLE_ARCH_riscv_TRUE@ $(am__DEPENDENCIES_1)
+am_rl78_run_OBJECTS =
+rl78_run_OBJECTS = $(am_rl78_run_OBJECTS)
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_DEPENDENCIES = rl78/main.o \
+@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/libsim.a $(am__DEPENDENCIES_1)
+am_rx_run_OBJECTS =
+rx_run_OBJECTS = $(am_rx_run_OBJECTS)
+@SIM_ENABLE_ARCH_rx_TRUE@rx_run_DEPENDENCIES = rx/main.o rx/libsim.a \
+@SIM_ENABLE_ARCH_rx_TRUE@ $(am__DEPENDENCIES_1)
@SIM_ENABLE_ARCH_sh_TRUE@am_sh_gencode_OBJECTS = sh/gencode.$(OBJEXT)
sh_gencode_OBJECTS = $(am_sh_gencode_OBJECTS)
sh_gencode_LDADD = $(LDADD)
+am_sh_run_OBJECTS =
+sh_run_OBJECTS = $(am_sh_run_OBJECTS)
+@SIM_ENABLE_ARCH_sh_TRUE@sh_run_DEPENDENCIES = sh/nrun.o sh/libsim.a \
+@SIM_ENABLE_ARCH_sh_TRUE@ $(am__DEPENDENCIES_1)
testsuite_common_alu_tst_SOURCES = testsuite/common/alu-tst.c
testsuite_common_alu_tst_OBJECTS = testsuite/common/alu-tst.$(OBJEXT)
testsuite_common_alu_tst_LDADD = $(LDADD)
testsuite_common_fpu_tst_SOURCES = testsuite/common/fpu-tst.c
testsuite_common_fpu_tst_OBJECTS = testsuite/common/fpu-tst.$(OBJEXT)
testsuite_common_fpu_tst_LDADD = $(LDADD)
+am_v850_run_OBJECTS =
+v850_run_OBJECTS = $(am_v850_run_OBJECTS)
+@SIM_ENABLE_ARCH_v850_TRUE@v850_run_DEPENDENCIES = v850/nrun.o \
+@SIM_ENABLE_ARCH_v850_TRUE@ v850/libsim.a $(am__DEPENDENCIES_1)
AM_V_P = $(am__v_P_@AM_V@)
am__v_P_ = $(am__v_P_@AM_DEFAULT_V@)
am__v_P_0 = false
am__v_CCLD_0 = @echo " CCLD " $@;
am__v_CCLD_1 =
SOURCES = $(common_libcommon_a_SOURCES) $(igen_libigen_a_SOURCES) \
- $(cr16_gencode_SOURCES) $(cris_rvdummy_SOURCES) \
- $(d10v_gencode_SOURCES) $(igen_filter_SOURCES) \
- $(igen_gen_SOURCES) $(igen_igen_SOURCES) \
- $(igen_ld_cache_SOURCES) $(igen_ld_decode_SOURCES) \
- $(igen_ld_insn_SOURCES) $(igen_table_SOURCES) \
- $(m32c_opc2c_SOURCES) $(m68hc11_gencode_SOURCES) \
- $(sh_gencode_SOURCES) testsuite/common/alu-tst.c \
+ $(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \
+ $(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \
+ $(cr16_run_SOURCES) $(cris_run_SOURCES) \
+ $(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \
+ $(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \
+ $(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
+ $(ft32_run_SOURCES) $(h8300_run_SOURCES) \
+ $(igen_filter_SOURCES) $(igen_gen_SOURCES) \
+ $(igen_igen_SOURCES) $(igen_ld_cache_SOURCES) \
+ $(igen_ld_decode_SOURCES) $(igen_ld_insn_SOURCES) \
+ $(igen_table_SOURCES) $(iq2000_run_SOURCES) \
+ $(lm32_run_SOURCES) $(m32c_opc2c_SOURCES) $(m32c_run_SOURCES) \
+ $(m32r_run_SOURCES) $(m68hc11_gencode_SOURCES) \
+ $(m68hc11_run_SOURCES) $(mcore_run_SOURCES) \
+ $(microblaze_run_SOURCES) $(mips_run_SOURCES) \
+ $(mn10300_run_SOURCES) $(moxie_run_SOURCES) \
+ $(msp430_run_SOURCES) $(or1k_run_SOURCES) ppc/psim.c \
+ $(ppc_run_SOURCES) $(pru_run_SOURCES) $(riscv_run_SOURCES) \
+ $(rl78_run_SOURCES) $(rx_run_SOURCES) $(sh_gencode_SOURCES) \
+ $(sh_run_SOURCES) testsuite/common/alu-tst.c \
testsuite/common/bits-gen.c testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
- testsuite/common/bits64m63.c testsuite/common/fpu-tst.c
+ testsuite/common/bits64m63.c testsuite/common/fpu-tst.c \
+ $(v850_run_SOURCES)
RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \
ctags-recursive dvi-recursive html-recursive info-recursive \
install-data-recursive install-dvi-recursive \
SUBDIRS = @subdirs@ $(SIM_SUBDIRS)
AM_MAKEFLAGS = SIM_PRIMARY_TARGET=$(SIM_PRIMARY_TARGET)
pkginclude_HEADERS = $(am__append_1)
-noinst_LIBRARIES = common/libcommon.a $(am__append_3)
+noinst_LIBRARIES = $(SIM_COMMON_LIB) $(am__append_3)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
testsuite/common/bits64m63.c
-DISTCLEANFILES = $(am__append_35)
+DISTCLEANFILES =
MOSTLYCLEANFILES = core $(am__append_5) site-sim-config.exp \
- testrun.log testrun.sum $(am__append_7) $(am__append_10) \
- $(am__append_13) $(am__append_16) $(am__append_20) \
- $(am__append_22) $(am__append_24) $(am__append_27) \
- $(am__append_29) $(am__append_32) $(am__append_34) \
- $(am__append_37) $(am__append_40) $(am__append_42)
+ testrun.log testrun.sum $(am__append_12) $(am__append_16) \
+ $(am__append_20) $(am__append_24) $(am__append_31) \
+ $(am__append_36) $(am__append_39) $(am__append_43) \
+ $(am__append_46) $(am__append_50) $(am__append_56) \
+ $(am__append_61) $(am__append_70) $(am__append_73)
AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
SIM_ALL_RECURSIVE_DEPS = common/libcommon.a $(am__append_2) \
- $(am__append_6) $(am__append_8) $(am__append_12) \
- $(am__append_14) $(am__append_19) $(am__append_21) \
- $(am__append_23) $(am__append_25) $(am__append_28) \
- $(am__append_30) $(am__append_33) $(am__append_36) \
- $(am__append_38) $(am__append_41)
+ $(am__append_11) $(am__append_14) $(am__append_19) \
+ $(am__append_22) $(am__append_30) $(am__append_35) \
+ $(am__append_38) $(am__append_41) $(am__append_45) \
+ $(am__append_48) $(am__append_55) $(am__append_60) \
+ $(am__append_68) $(am__append_72)
SIM_INSTALL_DATA_LOCAL_DEPS =
-SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_17)
-SIM_UNINSTALL_LOCAL_DEPS = $(am__append_18)
+SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_26)
+SIM_UNINSTALL_LOCAL_DEPS = $(am__append_27)
+SIM_COMMON_LIB = common/libcommon.a
common_libcommon_a_SOURCES = \
common/callback.c \
common/portability.c \
common/target-newlib-syscall.c \
common/version.c
+LIBIBERTY_LIB = ../libiberty/libiberty.a
+BFD_LIB = ../bfd/libbfd.la
+OPCODES_LIB = ../opcodes/libopcodes.la
+SIM_COMMON_LIBS = \
+ $(SIM_COMMON_LIB) \
+ $(BFD_LIB) \
+ $(OPCODES_LIB) \
+ $(LIBIBERTY_LIB) \
+ $(LIBGNU) \
+ $(LIBGNU_EXTRA_LIBS)
+
# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
-I$(srcroot)/include \
-I../bfd
+@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES =
+@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \
+@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/nrun.o \
+@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \
+@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES =
+@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \
+@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \
+@SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm
@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README
+@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES =
+@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/nrun.o \
+@SIM_ENABLE_ARCH_avr_TRUE@ avr/libsim.a \
+@SIM_ENABLE_ARCH_avr_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES =
+@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/nrun.o \
+@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/libsim.a \
+@SIM_ENABLE_ARCH_bfin_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/nrun.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-le.h \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.c \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.c \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-be
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES =
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/nrun.o \
+@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/libsim.a \
+@SIM_ENABLE_ARCH_cr16_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/simops.h \
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
+@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES =
+@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/nrun.o \
+@SIM_ENABLE_ARCH_cris_TRUE@ cris/libsim.a \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c
@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB)
@SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES =
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \
+@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/libsim.a \
+@SIM_ENABLE_ARCH_d10v_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.h \
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c
@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES =
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \
+@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/libsim.a \
+@SIM_ENABLE_ARCH_erc32_TRUE@ $(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB)
+
@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32
@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES =
+@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \
+@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \
+@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES =
+@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/nrun.o \
+@SIM_ENABLE_ARCH_frv_TRUE@ frv/libsim.a \
+@SIM_ENABLE_ARCH_frv_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv
@SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README
@SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.c \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/stamp-mloop
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES =
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/nrun.o \
+@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/libsim.a \
+@SIM_ENABLE_ARCH_ft32_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES =
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/nrun.o \
+@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/libsim.a \
+@SIM_ENABLE_ARCH_h8300_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES =
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/libsim.a \
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/eng.h \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \
@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES =
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \
+@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/libsim.a \
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/eng.h \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \
@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES =
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \
+@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/libsim.a \
+@SIM_ENABLE_ARCH_m32c_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/opc2c$(EXEEXT) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c \
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES =
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \
+@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/libsim.a \
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES =
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/libsim.a \
+@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode$(EXEEXT) \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.c \
@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES =
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \
+@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \
+@SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES =
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \
+@SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES =
+@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \
+@SIM_ENABLE_ARCH_mips_TRUE@ mips/libsim.a \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_COMMON_LIBS)
+
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES =
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/libsim.a \
+@SIM_ENABLE_ARCH_mn10300_TRUE@ $(SIM_COMMON_LIBS)
+
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.c \
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen
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projects / binutils-gdb.git / commitdiff