r600g: Move r600_pipe_shader_vs() to r600_state.c.

The idea behind this is that anything touching registers should be in
r600_state.c or evergreen_state.c. This is also consistent with
evergreen_pipe_shader_vs().

Signed-off-by: Henri Verbeet <hverbeet@gmail.com>

diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h
index 1b78c0907124fd4a6dff137f4d6456c073a12cc9..edbadc9a371be45d2960d0e79204fda1870d6b31 100644 (file)
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -215,6 +215,7 @@ int r600_find_vs_semantic_index(struct r600_shader *vs,
 void r600_init_state_functions(struct r600_pipe_context *rctx);
 void r600_spi_update(struct r600_pipe_context *rctx);
 void r600_init_config(struct r600_pipe_context *rctx);
+void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
 void r600_pipe_set_buffer_resource(struct r600_pipe_context *rctx,

diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c
index 383601416584bb15450bd9b35737eecc9cdf7bbc..3e87e24e5ffb1154c018f8aeca3bebb7e6f48c45 100644 (file)
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -34,55 +34,6 @@
 #include <stdio.h>
 #include <errno.h>
 
-static void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
-{
-       struct r600_pipe_state *rstate = &shader->rstate;
-       struct r600_shader *rshader = &shader->shader;
-       unsigned spi_vs_out_id[10];
-       unsigned i, tmp;
-
-       /* clear previous register */
-       rstate->nregs = 0;
-
-       /* so far never got proper semantic id from tgsi */
-       /* FIXME better to move this in config things so they get emited
-        * only one time per cs
-        */
-       for (i = 0; i < 10; i++) {
-               spi_vs_out_id[i] = 0;
-       }
-       for (i = 0; i < 32; i++) {
-               tmp = i << ((i & 3) * 8);
-               spi_vs_out_id[i / 4] |= tmp;
-       }
-       for (i = 0; i < 10; i++) {
-               r600_pipe_state_add_reg(rstate,
-                                       R_028614_SPI_VS_OUT_ID_0 + i * 4,
-                                       spi_vs_out_id[i], 0xFFFFFFFF, NULL);
-       }
-
-       r600_pipe_state_add_reg(rstate,
-                       R_0286C4_SPI_VS_OUT_CONFIG,
-                       S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
-                       0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate,
-                       R_028868_SQ_PGM_RESOURCES_VS,
-                       S_028868_NUM_GPRS(rshader->bc.ngpr) |
-                       S_028868_STACK_SIZE(rshader->bc.nstack),
-                       0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate,
-                       R_0288D0_SQ_PGM_CF_OFFSET_VS,
-                       0x00000000, 0xFFFFFFFF, NULL);
-       r600_pipe_state_add_reg(rstate,
-                       R_028858_SQ_PGM_START_VS,
-                       r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
-
-       r600_pipe_state_add_reg(rstate,
-                               R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
-                               0xFFFFFFFF, NULL);
-
-}
-
 int r600_find_vs_semantic_index(struct r600_shader *vs,
                                struct r600_shader *ps, int id)
 {

diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 200e8e45fc8b77c50e09cb81c13728f7f10a7f6c..994887069bf42abf27955a5f652518296131d183 100644 (file)
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1222,6 +1222,54 @@ void r600_init_config(struct r600_pipe_context *rctx)
        r600_context_pipe_state_set(&rctx->ctx, rstate);
 }
 
+void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
+{
+       struct r600_pipe_state *rstate = &shader->rstate;
+       struct r600_shader *rshader = &shader->shader;
+       unsigned spi_vs_out_id[10];
+       unsigned i, tmp;
+
+       /* clear previous register */
+       rstate->nregs = 0;
+
+       /* so far never got proper semantic id from tgsi */
+       /* FIXME better to move this in config things so they get emited
+        * only one time per cs
+        */
+       for (i = 0; i < 10; i++) {
+               spi_vs_out_id[i] = 0;
+       }
+       for (i = 0; i < 32; i++) {
+               tmp = i << ((i & 3) * 8);
+               spi_vs_out_id[i / 4] |= tmp;
+       }
+       for (i = 0; i < 10; i++) {
+               r600_pipe_state_add_reg(rstate,
+                                       R_028614_SPI_VS_OUT_ID_0 + i * 4,
+                                       spi_vs_out_id[i], 0xFFFFFFFF, NULL);
+       }
+
+       r600_pipe_state_add_reg(rstate,
+                       R_0286C4_SPI_VS_OUT_CONFIG,
+                       S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
+                       0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate,
+                       R_028868_SQ_PGM_RESOURCES_VS,
+                       S_028868_NUM_GPRS(rshader->bc.ngpr) |
+                       S_028868_STACK_SIZE(rshader->bc.nstack),
+                       0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate,
+                       R_0288D0_SQ_PGM_CF_OFFSET_VS,
+                       0x00000000, 0xFFFFFFFF, NULL);
+       r600_pipe_state_add_reg(rstate,
+                       R_028858_SQ_PGM_START_VS,
+                       r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
+
+       r600_pipe_state_add_reg(rstate,
+                               R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
+                               0xFFFFFFFF, NULL);
+}
+
 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
 {
        struct pipe_depth_stencil_alpha_state dsa;