[sim] fixed divw/remw crashing simulator

diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h
index 5bf4db0a511850264b30de200e9190a69dfd38df..51c3d8042f29d2361babd5d5db497f6b41657144 100644 (file)
--- a/riscv/insns/divw.h
+++ b/riscv/insns/divw.h
@@ -1,9 +1,7 @@
 require_xpr64;
 if(RS2 == 0)
   RD = UINT64_MAX;
-// INT64_MIN/-1 corner case shouldn't occur in correct code, since
-// INT64_MIN is not a proper 32-bit signed value
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
   RD = RS1;
 else
   RD = sext32(int32_t(RS1) / int32_t(RS2));

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index c338516cc1fa3a006e783884f60dd5e9e9efe0c9..93c38588efb48cbd0411030e7c1ac93a5b2f2dd2 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,9 +1,7 @@
 require_xpr64;
-// INT64_MIN/-1 corner case shouldn't occur in correct code, since
-// INT64_MIN is not a proper 32-bit signed value
 if(RS2 == 0)
   RD = RS1;
-else if(sreg_t(RS1) == INT64_MIN && sreg_t(RS2) == -1)
+else if(int32_t(RS1) == INT32_MIN && int32_t(RS2) == -1)
   RD = 0;
 else
   RD = sext32(int32_t(RS1) % int32_t(RS2));