arm: Squash after returning from exceptions in v7

Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.

diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index 8816764960171858f5f2ba639c03324bab5fc906..df5a8b51e924599b354cde169b0abe76356cf5e9 100644 (file)
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -273,10 +273,12 @@ let {{
             '''
             buildImmDataInst(mnem + 's', code, flagType,
                              suffix = "ImmPclr", buildCc = False,
-                             instFlags = ["IsSerializeAfter","IsNonSpeculative"])
+                             instFlags = ["IsSerializeAfter","IsNonSpeculative",
+                                          "IsSquashAfter"])
             buildRegDataInst(mnem + 's', code, flagType,
                              suffix = "RegPclr", buildCc = False,
-                             instFlags = ["IsSerializeAfter","IsNonSpeculative"])
+                             instFlags = ["IsSerializeAfter","IsNonSpeculative",
+                                          "IsSquashAfter"])
 
     buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
     buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")

diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 8c1b26808bd1217ba0d52253c57fbcc881f81343..cc7366e2bce4778486b099cb028de1aee58b5d0b 100644 (file)
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -124,7 +124,7 @@ let {{
                                           'EA = URb + (up ? imm : -imm);',
                                        'predicate_test': condPredicateTest},
                                       ['IsMicroop','IsNonSpeculative',
-                                       'IsSerializeAfter'])
+                                       'IsSerializeAfter', 'IsSquashAfter'])
 
     microStrUopCode = "Mem = cSwap(URa_uw, ((CPSR)Cpsr).e);"
     microStrUopIop = InstObjParams('str_uop', 'MicroStrUop',
@@ -668,7 +668,7 @@ let {{
                                      {'code': microRetUopCode % 'URb',
                                       'predicate_test': predicateTest},
                                      ['IsMicroop', 'IsNonSpeculative',
-                                      'IsSerializeAfter'])
+                                      'IsSerializeAfter', 'IsSquashAfter'])
 
     setPCCPSRDecl = '''
                     CPSR cpsrOrCondCodes = URc;

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index c8b1de1d8e5fe1f5747054edb1efa3ba91374bdf..77c22e6ca9ebde6e9b9e5381e30389ff8447392c 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -130,7 +130,8 @@ let {{
     eretIop = InstObjParams("eret", "Eret", "PredOp",
                            { "code": eretCode,
                              "predicate_test": predicateTest },
-                           ["IsNonSpeculative", "IsSerializeAfter"])
+                           ["IsNonSpeculative", "IsSerializeAfter",
+                            "IsSquashAfter"])
     header_output += BasicDeclare.subst(eretIop)
     decoder_output += BasicConstructor.subst(eretIop)
     exec_output += PredOpExecute.subst(eretIop)