genlib/fifo: support RecordP

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index afb397f83e279712e15107166da0be3004133bdc..b892e9c46ac8b241634c9da1cc22d0e98613ab6e 100644 (file)
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -19,18 +19,18 @@ class _FIFOInterface:
                self.re = Signal()
                self.readable = Signal() # not empty
 
-               if isinstance(width_or_layout, list):
-                       self.din = Record(width_or_layout)
-                       self.dout = Record(width_or_layout)
-                       self.din_bits = self.din.raw_bits()
-                       self.dout_bits = self.dout.raw_bits()
-                       self.width = layout_len(width_or_layout)
-               else:
+               if isinstance(width_or_layout, (int, tuple)):
                        self.din = Signal(width_or_layout)
                        self.dout = Signal(width_or_layout)
                        self.din_bits = self.din
                        self.dout_bits = self.dout
                        self.width = width_or_layout
+               else:
+                       self.din = Record(width_or_layout)
+                       self.dout = Record(width_or_layout)
+                       self.din_bits = self.din.raw_bits()
+                       self.dout_bits = self.dout.raw_bits()
+                       self.width = layout_len(width_or_layout)
 
 class SyncFIFO(Module, _FIFOInterface):
        def __init__(self, width_or_layout, depth):