Support command files in Verific

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 97930924807f1b1723b59181e553aa2274e17922..3e91673ac6b7a4f5b7dcd2410099c0f15c3e0b72 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -2084,6 +2084,11 @@ struct VerificPass : public Pass {
                log("Load the specified VHDL files into Verific.\n");
                log("\n");
                log("\n");
+               log("    verific {-f|-F} <command-file>\n");
+               log("\n");
+               log("Load and execute the specified command file.\n");
+               log("\n");
+               log("\n");
                log("    verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>\n");
                log("\n");
                log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n");
@@ -2407,6 +2412,25 @@ struct VerificPass : public Pass {
                        break;
                }
 
+               if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
+               {
+                       unsigned verilog_mode = veri_file::VERILOG_95; // default recommended by Verific
+
+                       Verific::veri_file::f_file_flags flags = (args[argidx] == "-f") ? veri_file::F_FILE_NONE : veri_file::F_FILE_CAPITAL;
+                       Array *file_names = veri_file::ProcessFFile(args[++argidx].c_str(), flags, verilog_mode);
+
+                       veri_file::DefineMacro("VERIFIC");
+
+                       if (!veri_file::AnalyzeMultipleFiles(file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
+                               verific_error_msg.clear();
+                               log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
+                       }
+
+                       delete file_names;
+                       verific_import_pending = true;
+                       goto check_error;
+               }
+
                if (GetSize(args) > argidx && (args[argidx] == "-vlog95" || args[argidx] == "-vlog2k" || args[argidx] == "-sv2005" ||
                                args[argidx] == "-sv2009" || args[argidx] == "-sv2012" || args[argidx] == "-sv" || args[argidx] == "-formal"))
                {
@@ -2963,6 +2987,11 @@ struct ReadPass : public Pass {
                log("Load the specified VHDL files. (Requires Verific.)\n");
                log("\n");
                log("\n");
+               log("    read {-f|-F} <command-file>\n");
+               log("\n");
+               log("Load and execute the specified command file. (Requires Verific.)\n");
+               log("\n");
+               log("\n");
                log("    read -define <macro>[=<value>]..\n");
                log("\n");
                log("Set global Verilog/SystemVerilog defines.\n");
@@ -3049,6 +3078,16 @@ struct ReadPass : public Pass {
                        return;
                }
 
+               if (args[1] == "-f" || args[1] == "-F") {
+                       if (use_verific) {
+                               args[0] = "verific";
+                               Pass::call(design, args);
+                       } else {
+                               cmd_error(args, 1, "This version of Yosys is built without Verific support.\n");
+                       }
+                       return;
+               }
+
                if (args[1] == "-define") {
                        if (use_verific) {
                                args[0] = "verific";