cpu/rocket: update submodule

diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
index bcb12b0233b050dddef8d9c69bbf590d10428647..b17b6984b9b7b0d0c259306ba94187abae7f37f5 160000 (submodule)
--- a/litex/soc/cores/cpu/rocket/verilog
+++ b/litex/soc/cores/cpu/rocket/verilog
@@ -1 +1 @@
-Subproject commit bcb12b0233b050dddef8d9c69bbf590d10428647
+Subproject commit b17b6984b9b7b0d0c259306ba94187abae7f37f5