i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.

I wanted to access this value from stage-generic code, so stop storing it
under two different names.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index c0cb26745ca032169e7367aea7c1f7da07460bf7..7aa9484f5688bdb418cda646b3a9b67bc8441a7b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -297,6 +297,12 @@ struct brw_stage_prog_data {
    GLuint nr_params;       /**< number of float params/constants */
    GLuint nr_pull_params;
 
+   /**
+    * Register where the thread expects to find input data from the URB
+    * (typically uniforms, followed by vertex or fragment attributes).
+    */
+   unsigned dispatch_grf_start_reg;
+
    /* Pointers to tracked values (only valid once
     * _mesa_load_state_parameters has been called at runtime).
     *
@@ -321,8 +327,7 @@ struct brw_wm_prog_data {
    GLuint curb_read_length;
    GLuint num_varying_inputs;
 
-   GLuint first_curbe_grf;
-   GLuint first_curbe_grf_16;
+   GLuint dispatch_grf_start_reg_16;
    GLuint reg_blocks;
    GLuint reg_blocks_16;
    GLuint total_scratch;
@@ -524,12 +529,6 @@ struct brw_vec4_prog_data {
    struct brw_stage_prog_data base;
    struct brw_vue_map vue_map;
 
-   /**
-    * Register where the thread expects to find input data from the URB
-    * (typically uniforms, followed by per-vertex inputs).
-    */
-   unsigned dispatch_grf_start_reg;
-
    GLuint curb_read_length;
    GLuint urb_read_length;
    GLuint total_grf;

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d22b1bf8574c640f51766ec2d510766c8dcfa434..8f20b681c98c2ab9dab4c7c18c18995bbdf0c6fb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1465,9 +1465,9 @@ void
 fs_visitor::assign_curb_setup()
 {
    if (dispatch_width == 8) {
-      prog_data->first_curbe_grf = payload.num_regs;
+      prog_data->base.dispatch_grf_start_reg = payload.num_regs;
    } else {
-      prog_data->first_curbe_grf_16 = payload.num_regs;
+      prog_data->dispatch_grf_start_reg_16 = payload.num_regs;
    }
 
    prog_data->curb_read_length = ALIGN(stage_prog_data->nr_params, 8) / 8;

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 69272970d3b9c63c5c88ee69522f738b921db817..d9cde25290cc2315be3c2facb65d5a43ad7a14ad 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1529,7 +1529,7 @@ vec4_vs_visitor::setup_attributes(int payload_reg)
 int
 vec4_visitor::setup_uniforms(int reg)
 {
-   prog_data->dispatch_grf_start_reg = reg;
+   prog_data->base.dispatch_grf_start_reg = reg;
 
    /* The pre-gen6 VS requires that some push constants get loaded no
     * matter what, or the GPU would hang.
@@ -1554,7 +1554,7 @@ vec4_visitor::setup_uniforms(int reg)
 
    stage_prog_data->nr_params = this->uniforms * 4;
 
-   prog_data->curb_read_length = reg - prog_data->dispatch_grf_start_reg;
+   prog_data->curb_read_length = reg - prog_data->base.dispatch_grf_start_reg;
 
    return reg;
 }

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index bc6d1e504d477d8cd8a345b332f2ff0d2c0c3a27..07e29a5d32f8fde2103bccdac63be9575f6625ce 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -98,7 +98,7 @@ vec4_instruction::get_src(const struct brw_vec4_prog_data *prog_data, int i)
       break;
 
    case UNIFORM:
-      brw_reg = stride(brw_vec4_grf(prog_data->dispatch_grf_start_reg +
+      brw_reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg +
                                     (src[i].reg + src[i].reg_offset) / 2,
                                    ((src[i].reg + src[i].reg_offset) % 2) * 4),
                       0, 4, 1);

diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c
index 7d5f51111ef8d6812c52940c2220fcdeb211fa97..a0710abcb0432c3f9cb666445858867a5d3d8eeb 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -96,7 +96,7 @@ brw_upload_vs_unit(struct brw_context *brw)
    vs->thread3.const_urb_entry_read_length
       = brw->vs.prog_data->base.curb_read_length;
    vs->thread3.dispatch_grf_start_reg =
-      brw->vs.prog_data->base.dispatch_grf_start_reg;
+      brw->vs.prog_data->base.base.dispatch_grf_start_reg;
    vs->thread3.urb_entry_read_offset = 0;
 
    /* BRW_NEW_CURBE_OFFSETS, _NEW_TRANSFORM, BRW_NEW_VERTEX_PROGRAM */

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 98b5185f22a705f83f190305208d614baafc04bc..84d39c1dedb8204f66cebcea2f538b88a5fd071b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -87,8 +87,8 @@ brw_upload_wm_unit(struct brw_context *brw)
        * only have one hardware field to program for both dispatch
        * widths.
        */
-      assert(brw->wm.prog_data->first_curbe_grf ==
-            brw->wm.prog_data->first_curbe_grf_16);
+      assert(brw->wm.prog_data->base.dispatch_grf_start_reg ==
+            brw->wm.prog_data->dispatch_grf_start_reg_16);
    }
 
    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */
@@ -134,7 +134,8 @@ brw_upload_wm_unit(struct brw_context *brw)
       wm->thread2.per_thread_scratch_space = 0;
    }
 
-   wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf;
+   wm->thread3.dispatch_grf_start_reg =
+      brw->wm.prog_data->base.dispatch_grf_start_reg;
    wm->thread3.urb_entry_read_length =
       brw->wm.prog_data->num_varying_inputs * 2;
    wm->thread3.urb_entry_read_offset = 0;

diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 62fbd6c6837820c8e83236b1512fefa3450a71f9..9d3c184246f55c68109608ad4266f91635b499d0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -186,7 +186,7 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+   OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
             (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 402d9c38635b743d38a6e3494f7a11771c323a30..042b47d1db54a8dee8e898314211929ff7d7aa01 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -69,7 +69,8 @@ gen6_upload_wm_push_constants(struct brw_context *brw)
         fprintf(stderr, "WM constants:\n");
         for (i = 0; i < prog_data->base.nr_params; i++) {
            if ((i & 7) == 0)
-              fprintf(stderr, "g%d: ", prog_data->first_curbe_grf + i / 8);
+              fprintf(stderr, "g%d: ",
+                       prog_data->base.dispatch_grf_start_reg + i / 8);
            fprintf(stderr, "%8f ", constants[i]);
            if ((i & 7) == 7)
               fprintf(stderr, "\n");
@@ -174,17 +175,17 @@ upload_wm_state(struct brw_context *brw)
 
       if (min_inv_per_frag == 1) {
          dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
-         dw4 |= (brw->wm.prog_data->first_curbe_grf <<
+         dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
                  GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
-         dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN6_WM_DISPATCH_START_GRF_SHIFT_2);
       } else
-         dw4 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw4 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                 GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
    }
    else {
       dw5 |= GEN6_WM_8_DISPATCH_ENABLE;
-      dw4 |= (brw->wm.prog_data->first_curbe_grf <<
+      dw4 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
               GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
    }
 

diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 30dfa6b87c6e17dbae8e447ac582b6f623e7ac55..5f66bc6f5e7f936aab7ebc9dab9401aba8bdfe8e 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -110,7 +110,7 @@ upload_gs_state(struct brw_context *brw)
          (prog_data->urb_read_length <<
           GEN6_GS_URB_READ_LENGTH_SHIFT) |
          (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
-         (prog_data->dispatch_grf_start_reg <<
+         (prog_data->base.dispatch_grf_start_reg <<
           GEN6_GS_DISPATCH_START_GRF_SHIFT);
 
       /* Note: the meaning of the GEN7_GS_REORDER_TRAILING bit changes between

diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 01be7567dde6ed51f99d5d322f67348c8b308766..fd8a78f1872815a1d74d63a1e0bbfb2baced2553 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -98,7 +98,7 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((brw->vs.prog_data->base.dispatch_grf_start_reg <<
+   OUT_BATCH((brw->vs.prog_data->base.base.dispatch_grf_start_reg <<
               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
             (brw->vs.prog_data->base.urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
             (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 078284101b48263e29d2510cc442067eaf1010d3..27a3f44cfc8fcda6cc554143aa498e866845a58b 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -227,17 +227,17 @@ upload_ps_state(struct brw_context *brw)
       dw4 |= GEN7_PS_16_DISPATCH_ENABLE;
       if (min_inv_per_frag == 1) {
          dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-         dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+         dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
-         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
       } else
-         dw5 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw5 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
    }
    else {
       dw4 |= GEN7_PS_8_DISPATCH_ENABLE;
-      dw5 |= (brw->wm.prog_data->first_curbe_grf <<
+      dw5 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
    }
 

diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c
index a0f933c091832c3a724c7b4ae85a69ed657f37e9..446edec21798e5e431756ab26245e2446f4f4618 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c
@@ -76,7 +76,7 @@ gen8_upload_gs_state(struct brw_context *brw)
                 (prog_data->urb_read_length <<
                  GEN6_GS_URB_READ_LENGTH_SHIFT) |
                 (0 << GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT) |
-                (prog_data->dispatch_grf_start_reg <<
+                (prog_data->base.dispatch_grf_start_reg <<
                  GEN6_GS_DISPATCH_START_GRF_SHIFT));
 
       /* DW7 */

diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 8b8d5ea77474d3b3a688456e4c4d1dc6c1bb6615..3d6d7f0f7a2956c7fb2b2a3bd11e8730c8837c89 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -199,17 +199,17 @@ upload_ps_state(struct brw_context *brw)
       dw6 |= GEN7_PS_16_DISPATCH_ENABLE;
       if (min_invocations_per_fragment == 1) {
          dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
-         dw7 |= (brw->wm.prog_data->first_curbe_grf <<
+         dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
-         dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
       } else {
-         dw7 |= (brw->wm.prog_data->first_curbe_grf_16 <<
+         dw7 |= (brw->wm.prog_data->dispatch_grf_start_reg_16 <<
                  GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
       }
    } else {
       dw6 |= GEN7_PS_8_DISPATCH_ENABLE;
-      dw7 |= (brw->wm.prog_data->first_curbe_grf <<
+      dw7 |= (brw->wm.prog_data->base.dispatch_grf_start_reg <<
               GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
    }
 

diff --git a/src/mesa/drivers/dri/i965/gen8_vs_state.c b/src/mesa/drivers/dri/i965/gen8_vs_state.c
index 638e216a469406428ae5c635e98ab9d472891788..f5e8dd3e4e81540f5cc546b7aac045296f668b19 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_vs_state.c
@@ -64,7 +64,7 @@ upload_vs_state(struct brw_context *brw)
       OUT_BATCH(0);
    }
 
-   OUT_BATCH((prog_data->dispatch_grf_start_reg <<
+   OUT_BATCH((prog_data->base.dispatch_grf_start_reg <<
               GEN6_VS_DISPATCH_START_GRF_SHIFT) |
              (prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
              (0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));