Test/fix d10v RTE instruction.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c9d2fbb698da2e08ee3cd86e7bd784d9fa65217e..5916f14127eed4b4faf14634faee60bac92c705a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+Thu Oct 23 21:13:37 1997  Fred Fish  <fnf@cygnus.com>
+ 
+        * d10v-opc.c (d10v_opcodes): Correct entry for RTE.
+ 
 Mon Dec  8 11:21:07 1997  Nick Clifton  <nickc@cygnus.com>
 
        * disassemble.c: Remove disasm_symaddr() function.

diff --git a/sim/testsuite/d10v-elf/.Sanitize b/sim/testsuite/d10v-elf/.Sanitize
index dcdaad8a1862bf69246e09b2b1da08a06435ce98..25ed0ae363510f42914ea1736bd002bf9efa6d2c 100644 (file)
--- a/sim/testsuite/d10v-elf/.Sanitize
+++ b/sim/testsuite/d10v-elf/.Sanitize
@@ -15,6 +15,7 @@ t-msbu.s
 t-rac.s
 t-rachi.s
 t-rep.s
+t-rte.s
 t-mulxu.s
 t-sub.s
 t-subi.s

diff --git a/sim/testsuite/d10v-elf/t-rte.s b/sim/testsuite/d10v-elf/t-rte.s
new file mode 100644 (file)
index 0000000..5ce31dd
--- /dev/null
+++ b/sim/testsuite/d10v-elf/t-rte.s
@@ -0,0 +1,18 @@
+.include "t-macros.i"
+
+       start
+
+       PSW_BITS = PSW_C|PSW_F0|PSW_F1
+       
+       ldi     r6, #success@word
+       mvtc    r6, bpc
+       ldi     r6, #PSW_BITS
+       mvtc    r6, bpsw
+
+test_rte:
+       RTE
+       exit47
+
+success:
+       checkpsw2 1 PSW_BITS
+       exit0