static inline void
gen6_3DSTATE_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_zs_surface *zs,
- bool aligned_8x4)
+ const struct ilo_state_zs *zs)
{
const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
dw[0] = cmd | (cmd_len - 2);
- dw[1] = zs->payload[0];
- dw[2] = 0;
- /* see ilo_gpe_init_zs_surface() */
+ /*
+ * see zs_set_gen6_3DSTATE_DEPTH_BUFFER() and
+ * zs_set_gen7_3DSTATE_DEPTH_BUFFER()
+ */
if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
+ dw[1] = zs->depth[0];
+ dw[2] = 0;
dw[3] = 0;
- dw[4] = (aligned_8x4) ? zs->dw_aligned_8x4 : zs->payload[2];
- dw[5] = zs->payload[3];
- dw[6] = zs->payload[4];
- dw[7] = zs->payload[5];
+ dw[4] = zs->depth[2];
+ dw[5] = zs->depth[3];
+ dw[6] = 0;
+ dw[7] = zs->depth[4];
dw[5] |= builder->mocs << GEN8_DEPTH_DW5_MOCS__SHIFT;
- if (zs->bo) {
- ilo_builder_batch_reloc64(builder, pos + 2, zs->bo,
- zs->payload[1], INTEL_RELOC_WRITE);
+ if (zs->depth_bo) {
+ ilo_builder_batch_reloc64(builder, pos + 2, zs->depth_bo,
+ zs->depth[1], (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
}
} else {
- dw[3] = (aligned_8x4) ? zs->dw_aligned_8x4 : zs->payload[2];
- dw[4] = zs->payload[3];
- dw[5] = zs->payload[4];
- dw[6] = zs->payload[5];
+ dw[1] = zs->depth[0];
+ dw[2] = 0;
+ dw[3] = zs->depth[2];
+ dw[4] = zs->depth[3];
+ dw[5] = 0;
+ dw[6] = zs->depth[4];
if (ilo_dev_gen(builder->dev) >= ILO_GEN(7))
dw[4] |= builder->mocs << GEN7_DEPTH_DW4_MOCS__SHIFT;
else
dw[6] |= builder->mocs << GEN6_DEPTH_DW6_MOCS__SHIFT;
- if (zs->bo) {
- ilo_builder_batch_reloc(builder, pos + 2, zs->bo,
- zs->payload[1], INTEL_RELOC_WRITE);
+ if (zs->depth_bo) {
+ ilo_builder_batch_reloc(builder, pos + 2, zs->depth_bo,
+ zs->depth[1], (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
}
}
}
static inline void
gen6_3DSTATE_STENCIL_BUFFER(struct ilo_builder *builder,
- const struct ilo_zs_surface *zs)
+ const struct ilo_state_zs *zs)
{
const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
dw[0] = cmd | (cmd_len - 2);
- /* see ilo_gpe_init_zs_surface() */
- dw[1] = zs->payload[6];
- dw[2] = 0;
+ /* see zs_set_gen6_3DSTATE_STENCIL_BUFFER() */
if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] |= builder->mocs << GEN8_STENCIL_DW1_MOCS__SHIFT;
-
+ dw[1] = zs->stencil[0];
+ dw[2] = 0;
dw[3] = 0;
- dw[4] = zs->payload[8];
+ dw[4] = zs->stencil[2];
- if (zs->separate_s8_bo) {
- ilo_builder_batch_reloc64(builder, pos + 2,
- zs->separate_s8_bo, zs->payload[7], INTEL_RELOC_WRITE);
+ dw[1] |= builder->mocs << GEN8_STENCIL_DW1_MOCS__SHIFT;
+
+ if (zs->stencil_bo) {
+ ilo_builder_batch_reloc64(builder, pos + 2, zs->stencil_bo,
+ zs->stencil[1], (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
}
} else {
+ dw[1] = zs->stencil[0];
+ dw[2] = 0;
+
dw[1] |= builder->mocs << GEN6_STENCIL_DW1_MOCS__SHIFT;
- if (zs->separate_s8_bo) {
- ilo_builder_batch_reloc(builder, pos + 2,
- zs->separate_s8_bo, zs->payload[7], INTEL_RELOC_WRITE);
+ if (zs->stencil_bo) {
+ ilo_builder_batch_reloc(builder, pos + 2, zs->stencil_bo,
+ zs->stencil[1], (zs->s_readonly) ? 0 : INTEL_RELOC_WRITE);
}
}
}
static inline void
gen6_3DSTATE_HIER_DEPTH_BUFFER(struct ilo_builder *builder,
- const struct ilo_zs_surface *zs)
+ const struct ilo_state_zs *zs)
{
const uint32_t cmd = (ilo_dev_gen(builder->dev) >= ILO_GEN(7)) ?
GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
pos = ilo_builder_batch_pointer(builder, cmd_len, &dw);
dw[0] = cmd | (cmd_len - 2);
- /* see ilo_gpe_init_zs_surface() */
- dw[1] = zs->payload[9];
- dw[2] = 0;
+ /* see zs_set_gen6_3DSTATE_HIER_DEPTH_BUFFER() */
if (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) {
- dw[1] |= builder->mocs << GEN8_HIZ_DW1_MOCS__SHIFT;
-
+ dw[1] = zs->hiz[0];
+ dw[2] = 0;
dw[3] = 0;
- dw[4] = zs->payload[11];
+ dw[4] = zs->hiz[2];
+
+ dw[1] |= builder->mocs << GEN8_HIZ_DW1_MOCS__SHIFT;
if (zs->hiz_bo) {
- ilo_builder_batch_reloc64(builder, pos + 2,
- zs->hiz_bo, zs->payload[10], INTEL_RELOC_WRITE);
+ ilo_builder_batch_reloc64(builder, pos + 2, zs->hiz_bo,
+ zs->hiz[1], (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
}
} else {
+ dw[1] = zs->hiz[0];
+ dw[2] = 0;
+
dw[1] |= builder->mocs << GEN6_HIZ_DW1_MOCS__SHIFT;
if (zs->hiz_bo) {
- ilo_builder_batch_reloc(builder, pos + 2,
- zs->hiz_bo, zs->payload[10], INTEL_RELOC_WRITE);
+ ilo_builder_batch_reloc(builder, pos + 2, zs->hiz_bo,
+ zs->hiz[1], (zs->z_readonly) ? 0 : INTEL_RELOC_WRITE);
}
}
}
if (ilo_debug & ILO_DEBUG_NOHIZ)
return false;
+ /* we want 8x4 aligned levels */
+ if (templ->target == PIPE_TEXTURE_1D)
+ return false;
+
if (!(templ->bind & PIPE_BIND_DEPTH_STENCIL))
return false;
#include "ilo_core.h"
#include "ilo_dev.h"
+#include "ilo_state_zs.h"
/**
* \see brw_context.h
bool is_rt;
union {
struct ilo_view_surface rt;
- struct ilo_zs_surface {
- uint32_t payload[12];
- uint32_t dw_aligned_8x4;
-
- struct intel_bo *bo;
- struct intel_bo *hiz_bo;
- struct intel_bo *separate_s8_bo;
- } zs;
+ struct ilo_state_zs zs;
} u;
};
struct pipe_framebuffer_state state;
struct ilo_view_surface null_rt;
- struct ilo_zs_surface null_zs;
+ struct ilo_state_zs null_zs;
struct ilo_fb_blend_caps {
bool can_logicop;
bool is_rt,
struct ilo_view_surface *surf);
-void
-ilo_gpe_init_zs_surface(const struct ilo_dev *dev,
- const struct ilo_image *img,
- const struct ilo_image *s8_img,
- enum pipe_format format, unsigned level,
- unsigned first_layer, unsigned num_layers,
- struct ilo_zs_surface *zs);
-
void
ilo_gpe_init_vs_cso(const struct ilo_dev *dev,
const struct ilo_shader_state *vs,
fs_init_cso_gen6(dev, fs, cso);
}
-struct ilo_zs_surface_info {
- int surface_type;
- int format;
-
- struct {
- struct intel_bo *bo;
- unsigned stride;
- unsigned qpitch;
- enum gen_surface_tiling tiling;
- uint32_t offset;
- } zs, stencil, hiz;
-
- unsigned width, height, depth;
- unsigned lod, first_layer, num_layers;
-};
-
-static void
-zs_init_info_null(const struct ilo_dev *dev,
- struct ilo_zs_surface_info *info)
-{
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(info, 0, sizeof(*info));
-
- info->surface_type = GEN6_SURFTYPE_NULL;
- info->format = GEN6_ZFORMAT_D32_FLOAT;
- info->width = 1;
- info->height = 1;
- info->depth = 1;
- info->num_layers = 1;
-}
-
-static void
-zs_init_info(const struct ilo_dev *dev,
- const struct ilo_image *img,
- const struct ilo_image *s8_img,
- enum pipe_format format, unsigned level,
- unsigned first_layer, unsigned num_layers,
- struct ilo_zs_surface_info *info)
-{
- bool separate_stencil;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- memset(info, 0, sizeof(*info));
-
- info->surface_type = ilo_gpe_gen6_translate_texture(img->target);
-
- if (info->surface_type == GEN6_SURFTYPE_CUBE) {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 325-326:
- *
- * "For Other Surfaces (Cube Surfaces):
- * This field (Minimum Array Element) is ignored."
- *
- * "For Other Surfaces (Cube Surfaces):
- * This field (Render Target View Extent) is ignored."
- *
- * As such, we cannot set first_layer and num_layers on cube surfaces.
- * To work around that, treat it as a 2D surface.
- */
- info->surface_type = GEN6_SURFTYPE_2D;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- separate_stencil = true;
- } else {
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 317:
- *
- * "This field (Separate Stencil Buffer Enable) must be set to the
- * same value (enabled or disabled) as Hierarchical Depth Buffer
- * Enable."
- */
- separate_stencil = ilo_image_can_enable_aux(img, level);
- }
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 317:
- *
- * "If this field (Hierarchical Depth Buffer Enable) is enabled, the
- * Surface Format of the depth buffer cannot be
- * D32_FLOAT_S8X24_UINT or D24_UNORM_S8_UINT. Use of stencil
- * requires the separate stencil buffer."
- *
- * From the Ironlake PRM, volume 2 part 1, page 330:
- *
- * "If this field (Separate Stencil Buffer Enable) is disabled, the
- * Surface Format of the depth buffer cannot be D24_UNORM_X8_UINT."
- *
- * There is no similar restriction for GEN6. But when D24_UNORM_X8_UINT
- * is indeed used, the depth values output by the fragment shaders will
- * be different when read back.
- *
- * As for GEN7+, separate_stencil is always true.
- */
- switch (format) {
- case PIPE_FORMAT_Z16_UNORM:
- info->format = GEN6_ZFORMAT_D16_UNORM;
- break;
- case PIPE_FORMAT_Z32_FLOAT:
- info->format = GEN6_ZFORMAT_D32_FLOAT;
- break;
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- info->format = (separate_stencil) ?
- GEN6_ZFORMAT_D24_UNORM_X8_UINT :
- GEN6_ZFORMAT_D24_UNORM_S8_UINT;
- break;
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- info->format = (separate_stencil) ?
- GEN6_ZFORMAT_D32_FLOAT :
- GEN6_ZFORMAT_D32_FLOAT_S8X24_UINT;
- break;
- case PIPE_FORMAT_S8_UINT:
- if (separate_stencil) {
- info->format = GEN6_ZFORMAT_D32_FLOAT;
- break;
- }
- /* fall through */
- default:
- assert(!"unsupported depth/stencil format");
- zs_init_info_null(dev, info);
- return;
- break;
- }
-
- if (format != PIPE_FORMAT_S8_UINT) {
- info->zs.bo = img->bo;
- info->zs.stride = img->bo_stride;
-
- assert(img->walk_layer_height % 4 == 0);
- info->zs.qpitch = img->walk_layer_height / 4;
-
- info->zs.tiling = img->tiling;
- info->zs.offset = 0;
- }
-
- if (s8_img || format == PIPE_FORMAT_S8_UINT) {
- info->stencil.bo = s8_img->bo;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 329:
- *
- * "The pitch must be set to 2x the value computed based on width,
- * as the stencil buffer is stored with two rows interleaved."
- *
- * For GEN7, we still dobule the stride because we did not double the
- * slice widths when initializing the layout.
- */
- info->stencil.stride = s8_img->bo_stride * 2;
-
- assert(s8_img->walk_layer_height % 4 == 0);
- info->stencil.qpitch = s8_img->walk_layer_height / 4;
-
- info->stencil.tiling = s8_img->tiling;
-
- if (ilo_dev_gen(dev) == ILO_GEN(6)) {
- unsigned x, y;
-
- assert(s8_img->walk == ILO_IMAGE_WALK_LOD);
-
- /* offset to the level */
- ilo_image_get_slice_pos(s8_img, level, 0, &x, &y);
- ilo_image_pos_to_mem(s8_img, x, y, &x, &y);
- info->stencil.offset = ilo_image_mem_to_raw(s8_img, x, y);
- }
- }
-
- if (ilo_image_can_enable_aux(img, level)) {
- info->hiz.bo = img->aux.bo;
- info->hiz.stride = img->aux.bo_stride;
-
- assert(img->aux.walk_layer_height % 4 == 0);
- info->hiz.qpitch = img->aux.walk_layer_height / 4;
-
- info->hiz.tiling = GEN6_TILING_Y;
-
- /* offset to the level */
- if (ilo_dev_gen(dev) == ILO_GEN(6))
- info->hiz.offset = img->aux.walk_lod_offsets[level];
- }
-
- info->width = img->width0;
- info->height = img->height0;
- info->depth = (img->target == PIPE_TEXTURE_3D) ? img->depth0 : num_layers;
-
- info->lod = level;
- info->first_layer = first_layer;
- info->num_layers = num_layers;
-}
-
-void
-ilo_gpe_init_zs_surface(const struct ilo_dev *dev,
- const struct ilo_image *img,
- const struct ilo_image *s8_img,
- enum pipe_format format, unsigned level,
- unsigned first_layer, unsigned num_layers,
- struct ilo_zs_surface *zs)
-{
- const int max_2d_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 16384 : 8192;
- const int max_array_size = (ilo_dev_gen(dev) >= ILO_GEN(7)) ? 2048 : 512;
- struct ilo_zs_surface_info info;
- uint32_t dw1, dw2, dw3, dw4, dw5, dw6;
- int align_w = 8, align_h = 4;
-
- ILO_DEV_ASSERT(dev, 6, 8);
-
- if (img) {
- zs_init_info(dev, img, s8_img, format,
- level, first_layer, num_layers, &info);
-
- switch (img->sample_count) {
- case 2:
- align_w /= 2;
- break;
- case 4:
- align_w /= 2;
- align_h /= 2;
- break;
- case 8:
- align_w /= 4;
- align_h /= 2;
- break;
- case 16:
- align_w /= 4;
- align_h /= 4;
- break;
- default:
- break;
- }
- } else {
- zs_init_info_null(dev, &info);
- }
-
- switch (info.surface_type) {
- case GEN6_SURFTYPE_NULL:
- break;
- case GEN6_SURFTYPE_1D:
- assert(info.width <= max_2d_size && info.height == 1 &&
- info.depth <= max_array_size);
- assert(info.first_layer < max_array_size - 1 &&
- info.num_layers <= max_array_size);
- break;
- case GEN6_SURFTYPE_2D:
- assert(info.width <= max_2d_size && info.height <= max_2d_size &&
- info.depth <= max_array_size);
- assert(info.first_layer < max_array_size - 1 &&
- info.num_layers <= max_array_size);
- break;
- case GEN6_SURFTYPE_3D:
- assert(info.width <= 2048 && info.height <= 2048 && info.depth <= 2048);
- assert(info.first_layer < 2048 && info.num_layers <= max_array_size);
- break;
- case GEN6_SURFTYPE_CUBE:
- assert(info.width <= max_2d_size && info.height <= max_2d_size &&
- info.depth == 1);
- assert(info.first_layer == 0 && info.num_layers == 1);
- assert(info.width == info.height);
- break;
- default:
- assert(!"unexpected depth surface type");
- break;
- }
-
- dw1 = info.surface_type << GEN6_DEPTH_DW1_TYPE__SHIFT |
- info.format << GEN6_DEPTH_DW1_FORMAT__SHIFT;
-
- if (info.zs.bo) {
- /* required for GEN6+ */
- assert(info.zs.tiling == GEN6_TILING_Y);
- assert(info.zs.stride > 0 && info.zs.stride < 128 * 1024 &&
- info.zs.stride % 128 == 0);
- assert(info.width <= info.zs.stride);
-
- dw1 |= (info.zs.stride - 1);
- dw2 = info.zs.offset;
- } else {
- dw2 = 0;
- }
-
- if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
- if (info.zs.bo)
- dw1 |= GEN7_DEPTH_DW1_DEPTH_WRITE_ENABLE;
-
- if (info.stencil.bo)
- dw1 |= GEN7_DEPTH_DW1_STENCIL_WRITE_ENABLE;
-
- if (info.hiz.bo)
- dw1 |= GEN7_DEPTH_DW1_HIZ_ENABLE;
-
- dw3 = (info.height - 1) << GEN7_DEPTH_DW3_HEIGHT__SHIFT |
- (info.width - 1) << GEN7_DEPTH_DW3_WIDTH__SHIFT |
- info.lod << GEN7_DEPTH_DW3_LOD__SHIFT;
-
- zs->dw_aligned_8x4 =
- (align(info.height, align_h) - 1) << GEN7_DEPTH_DW3_HEIGHT__SHIFT |
- (align(info.width, align_w) - 1) << GEN7_DEPTH_DW3_WIDTH__SHIFT |
- info.lod << GEN7_DEPTH_DW3_LOD__SHIFT;
-
- dw4 = (info.depth - 1) << GEN7_DEPTH_DW4_DEPTH__SHIFT |
- info.first_layer << GEN7_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT;
-
- dw5 = 0;
-
- dw6 = (info.num_layers - 1) << GEN7_DEPTH_DW6_RT_VIEW_EXTENT__SHIFT;
-
- if (ilo_dev_gen(dev) >= ILO_GEN(8))
- dw6 |= info.zs.qpitch;
- } else {
- /* always Y-tiled */
- dw1 |= GEN6_TILING_Y << GEN6_DEPTH_DW1_TILING__SHIFT;
-
- if (info.hiz.bo) {
- dw1 |= GEN6_DEPTH_DW1_HIZ_ENABLE |
- GEN6_DEPTH_DW1_SEPARATE_STENCIL;
- }
-
- dw3 = (info.height - 1) << GEN6_DEPTH_DW3_HEIGHT__SHIFT |
- (info.width - 1) << GEN6_DEPTH_DW3_WIDTH__SHIFT |
- info.lod << GEN6_DEPTH_DW3_LOD__SHIFT |
- GEN6_DEPTH_DW3_MIPLAYOUT_BELOW;
-
- zs->dw_aligned_8x4 =
- (align(info.height, align_h) - 1) << GEN6_DEPTH_DW3_HEIGHT__SHIFT |
- (align(info.width, align_w) - 1) << GEN6_DEPTH_DW3_WIDTH__SHIFT |
- info.lod << GEN6_DEPTH_DW3_LOD__SHIFT |
- GEN6_DEPTH_DW3_MIPLAYOUT_BELOW;
-
- dw4 = (info.depth - 1) << GEN6_DEPTH_DW4_DEPTH__SHIFT |
- info.first_layer << GEN6_DEPTH_DW4_MIN_ARRAY_ELEMENT__SHIFT |
- (info.num_layers - 1) << GEN6_DEPTH_DW4_RT_VIEW_EXTENT__SHIFT;
-
- dw5 = 0;
-
- dw6 = 0;
- }
-
- STATIC_ASSERT(Elements(zs->payload) >= 12);
-
- zs->payload[0] = dw1;
- zs->payload[1] = dw2;
- zs->payload[2] = dw3;
- zs->payload[3] = dw4;
- zs->payload[4] = dw5;
- zs->payload[5] = dw6;
-
- /* do not increment reference count */
- zs->bo = info.zs.bo;
-
- /* separate stencil */
- if (info.stencil.bo) {
- assert(info.stencil.stride > 0 && info.stencil.stride < 128 * 1024 &&
- info.stencil.stride % 128 == 0);
-
- dw1 = (info.stencil.stride - 1) << GEN6_STENCIL_DW1_PITCH__SHIFT;
- if (ilo_dev_gen(dev) >= ILO_GEN(7.5))
- dw1 |= GEN75_STENCIL_DW1_STENCIL_BUFFER_ENABLE;
-
- dw2 = info.stencil.offset;
- dw4 = info.stencil.qpitch;
- } else {
- dw1 = 0;
- dw2 = 0;
- dw4 = 0;
- }
-
- zs->payload[6] = dw1;
- zs->payload[7] = dw2;
- zs->payload[8] = dw4;
- /* do not increment reference count */
- zs->separate_s8_bo = info.stencil.bo;
-
- /* hiz */
- if (info.hiz.bo) {
- dw1 = (info.hiz.stride - 1) << GEN6_HIZ_DW1_PITCH__SHIFT;
- dw2 = info.hiz.offset;
- dw4 = info.hiz.qpitch;
- } else {
- dw1 = 0;
- dw2 = 0;
- dw4 = 0;
- }
-
- zs->payload[9] = dw1;
- zs->payload[10] = dw2;
- zs->payload[11] = dw4;
- /* do not increment reference count */
- zs->hiz_bo = info.hiz.bo;
-}
-
static void
viewport_get_guardband(const struct ilo_dev *dev,
int center_x, int center_y,
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_zs_surface *zs;
+ const struct ilo_state_zs *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
gen6_wa_pre_depth(r);
}
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false);
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen6_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
gen6_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL)) {
- gen6_3DSTATE_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs, true);
- }
+ ILO_BLITTER_USE_FB_STENCIL))
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_zs_surface *zs;
+ const struct ilo_state_zs *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
clear_params = 0;
}
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false);
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
gen7_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL)) {
- gen6_3DSTATE_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs, true);
- }
+ ILO_BLITTER_USE_FB_STENCIL))
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
if (DIRTY(FB) || r->batch_bo_changed) {
- const struct ilo_zs_surface *zs;
+ const struct ilo_state_zs *zs;
uint32_t clear_params;
if (vec->fb.state.zsbuf) {
gen8_wa_pre_depth(r);
- gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs, false);
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder, zs);
gen6_3DSTATE_STENCIL_BUFFER(r->builder, zs);
gen7_3DSTATE_CLEAR_PARAMS(r->builder, clear_params);
gen8_wa_pre_depth(r);
if (blitter->uses & (ILO_BLITTER_USE_FB_DEPTH |
- ILO_BLITTER_USE_FB_STENCIL)) {
- gen6_3DSTATE_DEPTH_BUFFER(r->builder,
- &blitter->fb.dst.u.zs, true);
- }
+ ILO_BLITTER_USE_FB_STENCIL))
+ gen6_3DSTATE_DEPTH_BUFFER(r->builder, &blitter->fb.dst.u.zs);
if (blitter->uses & ILO_BLITTER_USE_FB_DEPTH) {
gen6_3DSTATE_HIER_DEPTH_BUFFER(r->builder,
struct ilo_texture *tex = ilo_texture(res);
struct ilo_surface_cso *surf;
- surf = MALLOC_STRUCT(ilo_surface_cso);
+ surf = CALLOC_STRUCT(ilo_surface_cso);
assert(surf);
surf->base = *templ;
templ->u.tex.last_layer - templ->u.tex.first_layer + 1,
true, &surf->u.rt);
} else {
+ struct ilo_state_zs_info info;
+
assert(res->target != PIPE_BUFFER);
- ilo_gpe_init_zs_surface(dev, &tex->image,
- (tex->separate_s8) ? &tex->separate_s8->image : NULL,
- templ->format,
- templ->u.tex.level, templ->u.tex.first_layer,
- templ->u.tex.last_layer - templ->u.tex.first_layer + 1,
- &surf->u.zs);
+ memset(&info, 0, sizeof(info));
+
+ if (templ->format == PIPE_FORMAT_S8_UINT) {
+ info.s_img = &tex->image;
+ } else {
+ info.z_img = &tex->image;
+ info.s_img = (tex->separate_s8) ? &tex->separate_s8->image : NULL;
+
+ info.hiz_enable =
+ ilo_image_can_enable_aux(&tex->image, templ->u.tex.level);
+ }
+
+ info.level = templ->u.tex.level;
+ info.slice_base = templ->u.tex.first_layer;
+ info.slice_count = templ->u.tex.last_layer -
+ templ->u.tex.first_layer + 1;
+
+ ilo_state_zs_init(&surf->u.zs, dev, &info);
+
+ if (info.z_img) {
+ surf->u.zs.depth_bo = info.z_img->bo;
+ if (info.hiz_enable)
+ surf->u.zs.hiz_bo = info.z_img->aux.bo;
+ }
+
+ if (info.s_img)
+ surf->u.zs.stencil_bo = info.s_img->bo;
}
return &surf->base;
{
ilo_gpe_set_scissor_null(dev, &vec->scissor);
- ilo_gpe_init_zs_surface(dev, NULL, NULL,
- PIPE_FORMAT_NONE, 0, 0, 1, &vec->fb.null_zs);
+ ilo_state_zs_init_for_null(&vec->fb.null_zs, dev);
util_dynarray_init(&vec->global_binding.bindings);
struct ilo_surface_cso *cso =
(struct ilo_surface_cso *) vec->fb.state.zsbuf;
- cso->u.rt.bo = bo;
+ cso->u.zs.depth_bo = bo;
+
states |= ILO_DIRTY_FB;
}
}
projects / mesa.git / commitdiff