+2017-11-23 Charles Baylis <charles.baylis@linaro.org>
+
+ * config/arm/arm.c (arm_mem_costs): New function.
+ (arm_rtx_costs_internal): Use arm_mem_costs.
+
2017-11-23 Mark Wielaard <mark@klomp.org>
* dwarf2out.c (init_sections_and_labels): Use generation to create
} \
while (0)
+/* Helper function for arm_rtx_costs_internal. Calculates the cost of a MEM,
+ considering the costs of the addressing mode and memory access
+ separately. */
+static bool
+arm_mem_costs (rtx x, const struct cpu_cost_table *extra_cost,
+ int *cost, bool speed_p)
+{
+ machine_mode mode = GET_MODE (x);
+
+ *cost = COSTS_N_INSNS (1);
+
+ if (flag_pic
+ && GET_CODE (XEXP (x, 0)) == PLUS
+ && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
+ /* This will be split into two instructions. Add the cost of the
+ additional instruction here. The cost of the memory access is computed
+ below. See arm.md:calculate_pic_address. */
+ *cost += COSTS_N_INSNS (1);
+
+ /* Calculate cost of memory access. */
+ if (speed_p)
+ {
+ if (FLOAT_MODE_P (mode))
+ {
+ if (GET_MODE_SIZE (mode) == 8)
+ *cost += extra_cost->ldst.loadd;
+ else
+ *cost += extra_cost->ldst.loadf;
+ }
+ else if (VECTOR_MODE_P (mode))
+ *cost += extra_cost->ldst.loadv;
+ else
+ {
+ /* Integer modes */
+ if (GET_MODE_SIZE (mode) == 8)
+ *cost += extra_cost->ldst.ldrd;
+ else
+ *cost += extra_cost->ldst.load;
+ }
+ }
+
+ return true;
+}
+
/* RTX costs. Make an estimate of the cost of executing the operation
- X, which is contained with an operation with code OUTER_CODE.
+ X, which is contained within an operation with code OUTER_CODE.
SPEED_P indicates whether the cost desired is the performance cost,
or the size cost. The estimate is stored in COST and the return
value is TRUE if the cost calculation is final, or FALSE if the
return false;
case MEM:
- /* A memory access costs 1 insn if the mode is small, or the address is
- a single register, otherwise it costs one insn per word. */
- if (REG_P (XEXP (x, 0)))
- *cost = COSTS_N_INSNS (1);
- else if (flag_pic
- && GET_CODE (XEXP (x, 0)) == PLUS
- && will_be_in_index_register (XEXP (XEXP (x, 0), 1)))
- /* This will be split into two instructions.
- See arm.md:calculate_pic_address. */
- *cost = COSTS_N_INSNS (2);
- else
- *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode));
-
- /* For speed optimizations, add the costs of the address and
- accessing memory. */
- if (speed_p)
-#ifdef NOT_YET
- *cost += (extra_cost->ldst.load
- + arm_address_cost (XEXP (x, 0), mode,
- ADDR_SPACE_GENERIC, speed_p));
-#else
- *cost += extra_cost->ldst.load;
-#endif
- return true;
+ return arm_mem_costs (x, extra_cost, cost, speed_p);
case PARALLEL:
{
+2017-11-23 Charles Baylis <charles.baylis@linaro.org>
+
+ * gcc.target/arm/addr-modes-float.c: New test.
+ * gcc.target/arm/addr-modes-int.c: New test.
+ * gcc.target/arm/addr-modes.h: New header.
+
2017-11-23 Eric Botcazou <ebotcazou@adacore.com>
* testsuite/gcc.dg/pr64277.c: Adjust scan.
--- /dev/null
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-do compile } */
+
+#include <arm_neon.h>
+
+#include "addr-modes.h"
+
+POST_STORE(float)
+/* { dg-final { scan-assembler "vstmia.32" } } */
+POST_STORE(double)
+/* { dg-final { scan-assembler "vstmia.64" } } */
+
+POST_LOAD(float)
+/* { dg-final { scan-assembler "vldmia.32" } } */
+POST_LOAD(double)
+/* { dg-final { scan-assembler "vldmia.64" } } */
+
+POST_STORE_VEC (int8_t, int8x8_t, vst1_s8)
+/* { dg-final { scan-assembler "vst1.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */
+POST_STORE_VEC (int8_t, int8x16_t, vst1q_s8)
+/* { dg-final { scan-assembler "vst1.8\t\{.*\[-,\]d.*\}, \\\[r\[0-9\]+\\\]!" } } */
+
+POST_STORE_VEC (int8_t, int8x8x2_t, vst2_s8)
+/* { dg-final { scan-assembler "vst2.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */
+POST_STORE_VEC (int8_t, int8x16x2_t, vst2q_s8)
+/* { dg-final { scan-assembler "vst2.8\t\{.*-d.*\}, \\\[r\[0-9\]+\\\]!" } } */
+
+POST_STORE_VEC (int8_t, int8x8x3_t, vst3_s8)
+/* { dg-final { scan-assembler "vst3.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */
+POST_STORE_VEC (int8_t, int8x16x3_t, vst3q_s8)
+/* { dg-final { scan-assembler "vst3.8\t\{d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vst3.8\t\{d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */
+
+POST_STORE_VEC (int8_t, int8x8x4_t, vst4_s8)
+/* { dg-final { scan-assembler "vst4.8\t\{.*\}, \\\[r\[0-9\]+\\\]!" } } */
+POST_STORE_VEC (int8_t, int8x16x4_t, vst4q_s8)
+/* { dg-final { scan-assembler "vst4.8\t\{d\[02468\], d\[02468\], d\[02468\], d\[02468\]\}, \\\[r\[0-9\]+\\\]!" } } */
+/* { dg-final { scan-assembler "vst4.8\t\{d\[13579\], d\[13579\], d\[13579\], d\[13579\]\}, \\\[r\[0-9\]+\\\]!" { xfail *-*-* } } } */
+
+/* { dg-final { scan-assembler-not "add" { xfail *-*-* } } } */
--- /dev/null
+/* { dg-options "-O2 -march=armv7-a" } */
+/* { dg-add-options arm_neon } */
+/* { dg-require-effective-target arm_neon_ok } */
+/* { dg-do compile } */
+
+#include "addr-modes.h"
+
+typedef long long ll;
+
+PRE_STORE(char)
+/* { dg-final { scan-assembler "strb.*#1]!" } } */
+PRE_STORE(short)
+/* { dg-final { scan-assembler "strh.*#2]!" } } */
+PRE_STORE(int)
+/* { dg-final { scan-assembler "str.*#4]!" } } */
+PRE_STORE(ll)
+/* { dg-final { scan-assembler "strd.*#8]!" } } */
+
+POST_STORE(char)
+/* { dg-final { scan-assembler "strb.*], #1" } } */
+POST_STORE(short)
+/* { dg-final { scan-assembler "strh.*], #2" } } */
+POST_STORE(int)
+/* { dg-final { scan-assembler "str.*], #4" } } */
+POST_STORE(ll)
+/* { dg-final { scan-assembler "strd.*], #8" } } */
+
+PRE_LOAD(char)
+/* { dg-final { scan-assembler "ldrb.*#1]!" } } */
+PRE_LOAD(short)
+/* { dg-final { scan-assembler "ldrsh.*#2]!" } } */
+PRE_LOAD(int)
+/* { dg-final { scan-assembler "ldr.*#4]!" } } */
+PRE_LOAD(ll)
+/* { dg-final { scan-assembler "ldrd.*#8]!" } } */
+
+POST_LOAD(char)
+/* { dg-final { scan-assembler "ldrb.*], #1" } } */
+POST_LOAD(short)
+/* { dg-final { scan-assembler "ldrsh.*], #2" } } */
+POST_LOAD(int)
+/* { dg-final { scan-assembler "ldr.*], #4" } } */
+POST_LOAD(ll)
+/* { dg-final { scan-assembler "ldrd.*], #8" } } */
+
+/* { dg-final { scan-assembler-not "\tadd" } } */
--- /dev/null
+
+#define PRE_STORE(T) \
+ T * \
+ T ## _pre_store (T *p, T v) \
+ { \
+ *++p = v; \
+ return p; \
+ } \
+
+#define POST_STORE(T) \
+ T * \
+ T ## _post_store (T *p, T v) \
+ { \
+ *p++ = v; \
+ return p; \
+ }
+
+#define POST_STORE_VEC(T, VT, OP) \
+ T * \
+ VT ## _post_store (T * p, VT v) \
+ { \
+ OP (p, v); \
+ p += sizeof (VT) / sizeof (T); \
+ return p; \
+ }
+
+#define PRE_LOAD(T) \
+ void \
+ T ## _pre_load (T *p) \
+ { \
+ extern void f ## T (T*,T); \
+ T x = *++p; \
+ f ## T (p, x); \
+ }
+
+#define POST_LOAD(T) \
+ void \
+ T ## _post_load (T *p) \
+ { \
+ extern void f ## T (T*,T); \
+ T x = *p++; \
+ f ## T (p, x); \
+ }
+
+#define POST_LOAD_VEC(T, VT, OP) \
+ void \
+ VT ## _post_load (T * p) \
+ { \
+ extern void f ## T (T*,T); \
+ VT x = OP (p, v); \
+ p += sizeof (VT) / sizeof (T); \
+ f ## T (p, x); \
+ }
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