specials/Memory: allow for more flexibility in memory port signals

diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index ae0a2e63b44ad4d3b19cf9f5aff35b6f6147ce02..d048e1bffbd286ca270648638093e2b38c7045c0 100644 (file)
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -177,7 +177,10 @@ class _MemoryPort(Special):
                self.re = re
                self.we_granularity = we_granularity
                self.mode = mode
-               self.clock = ClockSignal(clock_domain)
+               if isinstance(clock_domain, str):
+                       self.clock = ClockSignal(clock_domain)
+               else:
+                       self.clock = clock_domain
 
        def iter_expressions(self):
                for attr, target_context in [
@@ -231,7 +234,11 @@ class Memory(Special):
        @staticmethod
        def emit_verilog(memory, ns):
                r = ""
-               gn = ns.get_name # usable instead of verilog_printexpr as ports contain only signals
+               def gn(e):
+                       if isinstance(e, Memory):
+                               return ns.get_name(e)
+                       else:
+                               return verilog_printexpr(ns, e)[0]
                adrbits = bits_for(memory.depth-1)
                
                r += "reg [" + str(memory.width-1) + ":0] " \