Add ssnop pattern.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0ac1cf14d94bfad06ed6082868b3ebbf97265528..6fe3353cba61f9d2ef1fd4d0a8b2bc60f74cb00b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+1999-11-11  Nick Clifton  <nickc@cygnus.com>
+
+       * mips-opc.c: Add ssnop pattern.
+
 1999-11-01  Gavin Romig-Koch  <gavin@cygnus.com>
 
        * mips-dis.c (_print_insn_mips): Use OPCODE_IS_MEMBER.

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b864619386350ad12c5bf1527e29807eb0da6de9..7be028caedb481adddba3f5e2325d51ba2ff399f 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -90,6 +90,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  *
 #define G3 (I4             \
             )
 
+#define M1      0
+#define M2      0
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -134,10 +137,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 /* bal is at the top of the table.  */
 {"bc0f",    "p",       0x41000000, 0xffff0000, CBD|RD_CC,      I1      },
 {"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,      I2|T3   },
-{"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1      },
-{"bc1f",    "N,p",     0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4      },
-{"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3   },
-{"bc1fl",   "N,p",     0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4      },
+{"bc1f",    "p",       0x45000000, 0xffff0000, CBD|RD_CC|FP_S, I1|M1   },
+{"bc1f",    "N,p",     0x45000000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1   },
+{"bc1fl",   "p",       0x45020000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3|M1},
+{"bc1fl",   "N,p",     0x45020000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1   },
 {"bc2f",    "p",       0x49000000, 0xffff0000, CBD|RD_CC,      I1      },
 {"bc2fl",   "p",       0x49020000, 0xffff0000, CBL|RD_CC,      I2|T3   },
 {"bc3f",    "p",       0x4d000000, 0xffff0000, CBD|RD_CC,      I1      },
@@ -227,6 +230,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"c.ueq.d", "M,S,T",   0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ueq.s", "S,T",     0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ueq.s", "M,S,T",   0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.lt.s",  "M,S,T",   0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.olt.d", "S,T",     0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.olt.d", "M,S,T",   0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
@@ -235,6 +240,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"c.ult.d", "M,S,T",   0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ult.s", "S,T",     0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ult.s", "M,S,T",   0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
+{"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
+{"c.le.s",  "M,S,T",   0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.ole.d", "S,T",     0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ole.d", "M,S,T",   0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ole.s", "S,T",     0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
@@ -261,21 +268,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"c.ngl.s", "M,S,T",   0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.lt.d",  "M,S,T",   0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
-{"c.lt.s",  "S,T",     0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.lt.s",  "M,S,T",   0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.nge.d", "M,S,T",   0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.nge.s", "S,T",     0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.nge.s", "M,S,T",   0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.le.d",  "M,S,T",   0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
-{"c.le.s",  "S,T",     0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
-{"c.le.s",  "M,S,T",   0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
 {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   I1      },
 {"c.ngt.d", "M,S,T",   0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   I4      },
 {"c.ngt.s", "S,T",     0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   I1      },
 {"c.ngt.s", "M,S,T",   0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   I4      },
-{"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3   },
+{"cache",   "k,o(b)",  0xbc000000, 0xfc000000, RD_b,           I3|T3|M1        },
 {"ceil.l.d", "D,S",    0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"ceil.l.s", "D,S",    0x4600000a, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"ceil.w.d", "D,S",    0x4620000e, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -310,7 +313,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 /* dctr and dctw are used on the r5000.  */
 {"dctr",    "o(b)",    0xbc050000, 0xfc1f0000, RD_b,   I3      },
 {"dctw",    "o(b)",    0xbc090000, 0xfc1f0000, RD_b,   I3      },
-{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2      },
+{"deret",   "",         0x4200001f, 0xffffffff,    0,  G2|M1   },
 /* For ddiv, see the comments about div.  */
 {"ddiv",    "z,s,t",   0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,  I3      },
 {"ddiv",    "d,v,t",   0,    (int) M_DDIV_3,   INSN_MACRO,     I3      },
@@ -381,7 +384,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,     I3      },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,     I3      },
-{"eret",    "",                0x42000018, 0xffffffff, 0,      I3      },
+{"eret",    "",                0x42000018, 0xffffffff, 0,      I3|M1   },
 {"floor.l.d", "D,S",   0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, I3      },
 {"floor.l.s", "D,S",   0x4600000b, 0xffff003f, WR_D|RD_S|FP_S, I3      },
 {"floor.w.d", "D,S",   0x4620000f, 0xffff003f, WR_D|RD_S|FP_D, I2      },
@@ -483,10 +486,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
 {"madd",    "s,t",     0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,             G1      },
+{"madd",    "s,t",     0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,             G1|M1   },
 {"madd",    "d,s,t",   0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1      },
 {"maddu",   "s,t",     0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO,          L1      },
-{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,     G1},
+{"maddu",   "s,t",     0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|IS_M,     G1|M1},
 {"maddu",   "d,s,t",   0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M,        G1},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO,     V1      },
 {"mfc0",    "t,G",     0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1      },
@@ -498,20 +501,20 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"mflo",    "d",       0x00000012, 0xffff07ff, WR_d|RD_LO,     I1      },
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D, I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S, I1      },
-{"movf",    "d,s,N",   0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S,      I4      },
-{"movf.d",  "D,S,N",   0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4      },
-{"movf.s",  "D,S,N",   0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4      },
-{"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4      },
+{"movf",    "d,s,N",   0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_D|FP_S, I4|M1},
+{"movf.d",  "D,S,N",   0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
+{"movf.s",  "D,S,N",   0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
+{"movn",    "d,v,t",   0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,L1    },
-{"movn.d",  "D,S,t",   0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4      },
-{"movn.s",  "D,S,t",   0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4      },
-{"movt",    "d,s,N",   0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4      },
-{"movt.d",  "D,S,N",   0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4      },
-{"movt.s",  "D,S,N",   0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4      },
-{"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4      },
+{"movn.d",  "D,S,t",   0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
+{"movn.s",  "D,S,t",   0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
+{"movt",    "d,s,N",   0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC,        I4|M1   },
+{"movt.d",  "D,S,N",   0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   I4|M1   },
+{"movt.s",  "D,S,N",   0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   I4|M1   },
+{"movz",    "d,v,t",   0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, I4|M1   },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,L1    },
-{"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4      },
-{"movz.s",  "D,S,t",   0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4      },
+{"movz.d",  "D,S,t",   0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    I4|M1   },
+{"movz.s",  "D,S,t",   0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    I4|M1   },
 /* move is at the top of the table.  */
 {"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,       I4      },
 {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,       I4      },
@@ -554,7 +557,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"ori",     "t,r,i",   0x34000000, 0xfc000000, WR_t|RD_s,      I1      },
 
 
-{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3      },
+{"pref",    "k,o(b)",  0xcc000000, 0xfc000000, RD_b,           G3|M1   },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t,      I4      },
 
 
@@ -586,9 +589,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"sd",     "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,   I3      },
 {"sd",      "t,o(b)",  0,    (int) M_SD_OB,    INSN_MACRO,     I1      },
 {"sd",      "t,A(b)",  0,    (int) M_SD_AB,    INSN_MACRO,     I1      },
-{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           G2      },
-{"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,           G2      },
-{"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,           G2      },
+{"sdbbp",   "",                0x0000000e, 0xffffffff, TRAP,           G2|M1   },
+{"sdbbp",   "c",       0x0000000e, 0xfc00ffff, TRAP,           G2|M1   },
+{"sdbbp",   "c,q",     0x0000000e, 0xfc00003f, TRAP,           G2|M1   },
 {"sdc1",    "T,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "E,o(b)",  0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      I2      },
 {"sdc1",    "T,A(b)",  0,    (int) M_SDC1_AB,  INSN_MACRO,     I2      },
@@ -642,6 +645,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"srlv",    "d,t,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1      },
 {"srl",     "d,w,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, I1      }, /* srlv */
 {"srl",     "d,w,<",   0x00000002, 0xffe0003f, WR_d|RD_t,      I1      },
+{"ssnop",     "",      0x00000040, 0xffffffff, 0,              M1      },
 {"standby", "",         0x42000021, 0xffffffff,        0,              V1      },
 {"sub",     "d,v,t",   0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,     I1      },
@@ -693,10 +697,10 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"tgeu",    "s,t,q",   0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
 {"tgeu",    "s,j",     0x04090000, 0xfc1f0000, RD_s|TRAP,      I2              }, /* tgeiu */
 {"tgeu",    "s,I",     0,    (int) M_TGEU_I,   INSN_MACRO,     I2      },
-{"tlbp",    "",                0x42000008, 0xffffffff, INSN_TLB,       I1      },
-{"tlbr",    "",                0x42000001, 0xffffffff, INSN_TLB,       I1      },
-{"tlbwi",   "",                0x42000002, 0xffffffff, INSN_TLB,       I1      },
-{"tlbwr",   "",                0x42000006, 0xffffffff, INSN_TLB,       I1      },
+{"tlbp",    "",                0x42000008, 0xffffffff, INSN_TLB,       I1|M1   },
+{"tlbr",    "",                0x42000001, 0xffffffff, INSN_TLB,       I1|M1   },
+{"tlbwi",   "",                0x42000002, 0xffffffff, INSN_TLB,       I1|M1   },
+{"tlbwr",   "",                0x42000006, 0xffffffff, INSN_TLB,       I1|M1   },
 {"tlti",    "s,j",     0x040a0000, 0xfc1f0000, RD_s|TRAP,      I2              },
 {"tlt",     "s,t",     0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, I2       },
 {"tlt",     "s,t,q",   0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, I2       },
@@ -737,7 +741,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,     I1      },
 {"xori",    "t,r,i",   0x38000000, 0xfc000000, WR_t|RD_s,      I1      },
-{"wait",    "",                0x42000020, 0xffffffff, TRAP,   I3      },
+{"wait",    "",                0x42000020, 0xffffffff, TRAP,   I3|M1   },
 {"waiti",   "",                0x42000020, 0xffffffff, TRAP,   L1      },
 {"wb",             "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,        L1      },
 /* No hazard protection on coprocessor instructions--they shouldn't