D is 25 bits not 24 bits wide

diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v
index 8901b215bd8f41f798430a8d59341eeb6e2b4ed5..a4256eb928cb2bcb6c169e71af4805be410aa620 100644 (file)
--- a/techlibs/xilinx/dsp_map.v
+++ b/techlibs/xilinx/dsp_map.v
@@ -32,7 +32,7 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
                .A({{5{A[24]}}, A}),
                .B(B),
                .C(48'b0),
-               .D(24'b0),
+               .D(25'b0),
                .P(P_48),
 
                .INMODE(5'b00000),