add test_read / test_write (HOST<-->HDD transfers OK for the 3 tests, rx data seems...

diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py
index 4dae7d591ee404d60af48614fd67afa833e7e591..1027f43401cb57ca5956270fe313d9f4814fbfa5 100644 (file)
--- a/lib/sata/command/__init__.py
+++ b/lib/sata/command/__init__.py
@@ -146,6 +146,8 @@ class SATACommandRX(Module):
                                If(test_type("DMA_ACTIVATE_D2H"),
                                        dma_activate.eq(1),
                                        NextState("WAIT_WRITE_REG_D2H")
+                               ).Else(
+                                       NextState("IDLE") # Generate an error
                                )
                        )
                )
@@ -154,6 +156,8 @@ class SATACommandRX(Module):
                        If(transport.source.stb,
                                If(test_type("REG_D2H"),
                                        NextState("PRESENT_WRITE_RESPONSE")
+                               ).Else(
+                                       NextState("IDLE") # Generate an error
                                )
                        )
                )
@@ -171,6 +175,8 @@ class SATACommandRX(Module):
                                transport.source.ack.eq(0),
                                If(test_type("DATA"),
                                        NextState("PRESENT_READ_DATA")
+                               ).Else(
+                                       NextState("IDLE") # Generate an error
                                )
                        )
                )
@@ -189,6 +195,8 @@ class SATACommandRX(Module):
                        If(transport.source.stb,
                                If(test_type("REG_D2H"),
                                        NextState("PRESENT_READ_RESPONSE")
+                               ).Else(
+                                       NextState("IDLE") # Generate an error
                                )
                        )
                )

diff --git a/test/test_identify.py b/test/test_identify.py
index 11cb91cfb20be6ce71433b721556ac76716dc751..24f1a4de4c5ae4dc1f61800c87d5e184a2a35957 100644 (file)
--- a/test/test_identify.py
+++ b/test/test_identify.py
@@ -7,11 +7,15 @@ mila = MiLaDriver(wb.regs, "mila")
 wb.open()
 regs = wb.regs
 ###
+
+#trigger0 = mila.sata_con_sink_payload_identify_o*1
+#mask0 = mila.sata_con_sink_payload_identify_m
+
 #trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
 #mask0 = mila.sata_phy_source_source_payload_data_m
 
-trigger0 = mila.sata_con_sink_payload_identify_o*1
-mask0 = mila.sata_con_sink_payload_identify_m
+trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
+mask0 = mila.sata_phy_source_source_payload_data_m
 
 mila.prog_term(port=0, trigger=trigger0, mask=mask0)
 mila.prog_sum("term")

diff --git a/test/test_read.py b/test/test_read.py
new file mode 100644 (file)
index 0000000..155c548
--- /dev/null
+++ b/test/test_read.py
@@ -0,0 +1,37 @@
+import time
+from config import *
+from tools import *
+from miscope.host.drivers import MiLaDriver
+
+mila = MiLaDriver(wb.regs, "mila")
+wb.open()
+regs = wb.regs
+###
+
+#trigger0 = mila.sata_con_sink_payload_read_o*1
+#mask0 = mila.sata_con_sink_payload_read_m
+
+#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
+#mask0 = mila.sata_phy_source_source_payload_data_m
+
+trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["X_RDY"]
+mask0 = mila.sata_phy_source_source_payload_data_m
+
+mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_sum("term")
+
+# Trigger / wait / receive
+mila.trigger(offset=32, length=512)
+regs.command_generator_sector.write(0)
+regs.command_generator_count.write(1)
+regs.command_generator_read.write(1)
+mila.wait_done()
+mila.read()
+mila.export("dump.vcd")
+###
+wb.close()
+
+print_link_trace(mila,
+       tx_data_name="sata_phy_sink_sink_payload_data",
+       rx_data_name="sata_phy_source_source_payload_data"
+)

diff --git a/test/test_write.py b/test/test_write.py
new file mode 100644 (file)
index 0000000..8c760d5
--- /dev/null
+++ b/test/test_write.py
@@ -0,0 +1,38 @@
+import time
+from config import *
+from tools import *
+from miscope.host.drivers import MiLaDriver
+
+mila = MiLaDriver(wb.regs, "mila")
+wb.open()
+regs = wb.regs
+###
+
+#trigger0 = mila.sata_con_sink_payload_write_o*1
+#mask0 = mila.sata_con_sink_payload_write_m
+
+#trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_RDY"]
+#mask0 = mila.sata_phy_source_source_payload_data_m
+
+trigger0 = mila.sata_phy_source_source_payload_data_o*primitives["R_OK"]
+mask0 = mila.sata_phy_source_source_payload_data_m
+
+mila.prog_term(port=0, trigger=trigger0, mask=mask0)
+mila.prog_sum("term")
+
+# Trigger / wait / receive
+mila.trigger(offset=32, length=512)
+regs.command_generator_sector.write(0)
+regs.command_generator_count.write(1)
+regs.command_generator_data.write(0x12345678)
+regs.command_generator_write.write(1)
+mila.wait_done()
+mila.read()
+mila.export("dump.vcd")
+###
+wb.close()
+
+print_link_trace(mila,
+       tx_data_name="sata_phy_sink_sink_payload_data",
+       rx_data_name="sata_phy_source_source_payload_data"
+)