//--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:11
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:26
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire ddram_reset_n,
output wire init_done,
output wire init_error,
- input wire [13:0] csr_port0_adr,
- input wire csr_port0_we,
- input wire [31:0] csr_port0_dat_w,
- output wire [31:0] csr_port0_dat_r,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
output wire user_clk,
output wire user_rst,
input wire user_port_native_0_cmd_valid,
output wire [127:0] user_port_native_0_rdata_data
);
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+wire [31:0] litedramcore_dat_w;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+wire [31:0] litedramcore_wishbone_dat_r;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire [7:0] a7ddrphy_dq_i_data0;
wire [7:0] a7ddrphy_bitslip0_i;
reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip0_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip0_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip0_r = 24'd0;
wire a7ddrphy_dq_o_nodelay1;
wire a7ddrphy_dq_i_nodelay1;
wire a7ddrphy_dq_i_delayed1;
wire [7:0] a7ddrphy_dq_i_data1;
wire [7:0] a7ddrphy_bitslip1_i;
reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip1_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip1_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip1_r = 24'd0;
wire a7ddrphy_dq_o_nodelay2;
wire a7ddrphy_dq_i_nodelay2;
wire a7ddrphy_dq_i_delayed2;
wire [7:0] a7ddrphy_dq_i_data2;
wire [7:0] a7ddrphy_bitslip2_i;
reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip2_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip2_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip2_r = 24'd0;
wire a7ddrphy_dq_o_nodelay3;
wire a7ddrphy_dq_i_nodelay3;
wire a7ddrphy_dq_i_delayed3;
wire [7:0] a7ddrphy_dq_i_data3;
wire [7:0] a7ddrphy_bitslip3_i;
reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip3_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip3_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip3_r = 24'd0;
wire a7ddrphy_dq_o_nodelay4;
wire a7ddrphy_dq_i_nodelay4;
wire a7ddrphy_dq_i_delayed4;
wire [7:0] a7ddrphy_dq_i_data4;
wire [7:0] a7ddrphy_bitslip4_i;
reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip4_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip4_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip4_r = 24'd0;
wire a7ddrphy_dq_o_nodelay5;
wire a7ddrphy_dq_i_nodelay5;
wire a7ddrphy_dq_i_delayed5;
wire [7:0] a7ddrphy_dq_i_data5;
wire [7:0] a7ddrphy_bitslip5_i;
reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip5_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip5_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip5_r = 24'd0;
wire a7ddrphy_dq_o_nodelay6;
wire a7ddrphy_dq_i_nodelay6;
wire a7ddrphy_dq_i_delayed6;
wire [7:0] a7ddrphy_dq_i_data6;
wire [7:0] a7ddrphy_bitslip6_i;
reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip6_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip6_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip6_r = 24'd0;
wire a7ddrphy_dq_o_nodelay7;
wire a7ddrphy_dq_i_nodelay7;
wire a7ddrphy_dq_i_delayed7;
wire [7:0] a7ddrphy_dq_i_data7;
wire [7:0] a7ddrphy_bitslip7_i;
reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip7_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip7_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip7_r = 24'd0;
wire a7ddrphy_dq_o_nodelay8;
wire a7ddrphy_dq_i_nodelay8;
wire a7ddrphy_dq_i_delayed8;
wire [7:0] a7ddrphy_dq_i_data8;
wire [7:0] a7ddrphy_bitslip8_i;
reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip8_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip8_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip8_r = 24'd0;
wire a7ddrphy_dq_o_nodelay9;
wire a7ddrphy_dq_i_nodelay9;
wire a7ddrphy_dq_i_delayed9;
wire [7:0] a7ddrphy_dq_i_data9;
wire [7:0] a7ddrphy_bitslip9_i;
reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip9_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip9_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip9_r = 24'd0;
wire a7ddrphy_dq_o_nodelay10;
wire a7ddrphy_dq_i_nodelay10;
wire a7ddrphy_dq_i_delayed10;
wire [7:0] a7ddrphy_dq_i_data10;
wire [7:0] a7ddrphy_bitslip10_i;
reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip10_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip10_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip10_r = 24'd0;
wire a7ddrphy_dq_o_nodelay11;
wire a7ddrphy_dq_i_nodelay11;
wire a7ddrphy_dq_i_delayed11;
wire [7:0] a7ddrphy_dq_i_data11;
wire [7:0] a7ddrphy_bitslip11_i;
reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip11_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip11_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip11_r = 24'd0;
wire a7ddrphy_dq_o_nodelay12;
wire a7ddrphy_dq_i_nodelay12;
wire a7ddrphy_dq_i_delayed12;
wire [7:0] a7ddrphy_dq_i_data12;
wire [7:0] a7ddrphy_bitslip12_i;
reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip12_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip12_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip12_r = 24'd0;
wire a7ddrphy_dq_o_nodelay13;
wire a7ddrphy_dq_i_nodelay13;
wire a7ddrphy_dq_i_delayed13;
wire [7:0] a7ddrphy_dq_i_data13;
wire [7:0] a7ddrphy_bitslip13_i;
reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip13_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip13_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip13_r = 24'd0;
wire a7ddrphy_dq_o_nodelay14;
wire a7ddrphy_dq_i_nodelay14;
wire a7ddrphy_dq_i_delayed14;
wire [7:0] a7ddrphy_dq_i_data14;
wire [7:0] a7ddrphy_bitslip14_i;
reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip14_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip14_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip14_r = 24'd0;
wire a7ddrphy_dq_o_nodelay15;
wire a7ddrphy_dq_i_nodelay15;
wire a7ddrphy_dq_i_delayed15;
wire [7:0] a7ddrphy_dq_i_data15;
wire [7:0] a7ddrphy_bitslip15_i;
reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip15_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip15_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip15_r = 24'd0;
wire [7:0] a7ddrphy_rddata_en;
reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
wire [3:0] a7ddrphy_wrdata_en;
reg init_done_re = 1'd0;
reg init_error_storage = 1'd0;
reg init_error_re = 1'd0;
-wire [13:0] csr_port_adr;
-wire csr_port_we;
-wire [31:0] csr_port_dat_w;
-wire [31:0] csr_port_dat_r;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
wire user_port_rdata_valid;
wire user_port_rdata_ready;
wire [127:0] user_port_rdata_payload_data;
+reg state = 1'd0;
+reg next_state = 1'd0;
wire pll_fb0;
wire pll_fb1;
reg [1:0] refresher_state = 2'd0;
// synthesis translate_on
assign init_done = init_done_storage;
assign init_error = init_error_storage;
-assign csr_port_adr = csr_port0_adr;
-assign csr_port_we = csr_port0_we;
-assign csr_port_dat_w = csr_port0_dat_w;
-assign csr_port0_dat_r = csr_port_dat_r;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign user_port_cmd_valid = user_port_native_0_cmd_valid;
assign user_port_native_0_rdata_valid = user_port_rdata_valid;
assign user_port_rdata_ready = user_port_native_0_rdata_ready;
assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
+assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+ next_state <= 1'd0;
+ next_state <= state;
+ case (state)
+ 1'd1: begin
+ next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ next_state <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_1 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_adr <= 14'd0;
+ case (state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_2 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_we <= 1'd0;
+ case (state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we <= litedramcore_wishbone_we;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_3 = dummy_s;
+// synthesis translate_on
+end
assign sys_pll_reset = rst;
assign pll_locked = sys_pll_locked;
assign iodelay_pll_reset = rst;
assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
// synthesis translate_off
-reg dummy_d;
+reg dummy_d_4;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p0_rddata <= 32'd0;
a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
// synthesis translate_off
- dummy_d = dummy_s;
+ dummy_d_4 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_1;
+reg dummy_d_5;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p1_rddata <= 32'd0;
a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
// synthesis translate_off
- dummy_d_1 = dummy_s;
+ dummy_d_5 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_2;
+reg dummy_d_6;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p2_rddata <= 32'd0;
a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
// synthesis translate_off
- dummy_d_2 = dummy_s;
+ dummy_d_6 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_3;
+reg dummy_d_7;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p3_rddata <= 32'd0;
a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
// synthesis translate_off
- dummy_d_3 = dummy_s;
+ dummy_d_7 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
// synthesis translate_off
-reg dummy_d_4;
+reg dummy_d_8;
// synthesis translate_on
always @(*) begin
a7ddrphy_dqs_oe <= 1'd0;
a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
end
// synthesis translate_off
- dummy_d_4 = dummy_s;
+ dummy_d_8 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
// synthesis translate_off
-reg dummy_d_5;
+reg dummy_d_9;
// synthesis translate_on
always @(*) begin
a7ddrphy_dqspattern_o0 <= 8'd0;
end
end
// synthesis translate_off
- dummy_d_5 = dummy_s;
+ dummy_d_9 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_6;
+reg dummy_d_10;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip0_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_6 = dummy_s;
+ dummy_d_10 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_7;
+reg dummy_d_11;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip1_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_7 = dummy_s;
+ dummy_d_11 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_8;
+reg dummy_d_12;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip2_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_8 = dummy_s;
+ dummy_d_12 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_9;
+reg dummy_d_13;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip3_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_9 = dummy_s;
+ dummy_d_13 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_10;
+reg dummy_d_14;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip4_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_10 = dummy_s;
+ dummy_d_14 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_11;
+reg dummy_d_15;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip5_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_11 = dummy_s;
+ dummy_d_15 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_12;
+reg dummy_d_16;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip6_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_12 = dummy_s;
+ dummy_d_16 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_13;
+reg dummy_d_17;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip7_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_13 = dummy_s;
+ dummy_d_17 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_14;
+reg dummy_d_18;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip8_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_14 = dummy_s;
+ dummy_d_18 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_15;
+reg dummy_d_19;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip9_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_15 = dummy_s;
+ dummy_d_19 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_16;
+reg dummy_d_20;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip10_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_16 = dummy_s;
+ dummy_d_20 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_17;
+reg dummy_d_21;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip11_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
end
- endcase
-// synthesis translate_off
- dummy_d_17 = dummy_s;
-// synthesis translate_on
-end
-
+ 4'd8: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15];
+ end
+ endcase
// synthesis translate_off
-reg dummy_d_18;
+ dummy_d_21 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_22;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip12_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_18 = dummy_s;
+ dummy_d_22 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_19;
+reg dummy_d_23;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip13_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_19 = dummy_s;
+ dummy_d_23 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_20;
+reg dummy_d_24;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip14_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_20 = dummy_s;
+ dummy_d_24 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_21;
+reg dummy_d_25;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip15_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_21 = dummy_s;
+ dummy_d_25 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
- end
-// synthesis translate_off
- dummy_d_22 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
- end
-// synthesis translate_off
- dummy_d_23 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
- end
-// synthesis translate_off
- dummy_d_24 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
- end
-// synthesis translate_off
- dummy_d_25 = dummy_s;
-// synthesis translate_on
-end
-
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
+ litedramcore_master_p2_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
+ litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_26 = dummy_s;
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata <= 32'd0;
+ litedramcore_master_p2_odt <= 1'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
end else begin
- litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
end
// synthesis translate_off
dummy_d_27 = dummy_s;
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
+ litedramcore_master_p2_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
+ litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_28 = dummy_s;
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata_valid <= 1'd0;
+ litedramcore_master_p2_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
end else begin
- litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
end
// synthesis translate_off
dummy_d_29 = dummy_s;
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
+ litedramcore_master_p2_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
+ litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
dummy_d_30 = dummy_s;
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
+ litedramcore_inti_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
+ litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_31 = dummy_s;
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_address <= 14'd0;
+ litedramcore_master_p2_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p0_address <= litedramcore_inti_p0_address;
+ litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
dummy_d_32 = dummy_s;
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
+ litedramcore_inti_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
end else begin
- litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_33 = dummy_s;
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
dummy_d_34 = dummy_s;
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
+ litedramcore_master_p2_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_35 = dummy_s;
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
+ litedramcore_master_p3_address <= 14'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
end else begin
+ litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_36 = dummy_s;
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
+ litedramcore_master_p3_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_37 = dummy_s;
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
+ litedramcore_master_p3_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_38 = dummy_s;
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
+ litedramcore_master_p3_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_39 = dummy_s;
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
+ litedramcore_master_p3_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
dummy_d_40 = dummy_s;
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
+ litedramcore_slave_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
end else begin
- litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_41 = dummy_s;
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
+ litedramcore_master_p3_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
end
// synthesis translate_off
dummy_d_42 = dummy_s;
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end else begin
- litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_43 = dummy_s;
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
+ litedramcore_master_p3_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
end
// synthesis translate_off
dummy_d_44 = dummy_s;
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata <= 32'd0;
+ litedramcore_master_p3_odt <= 1'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
end else begin
- litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+ litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
end
// synthesis translate_off
dummy_d_45 = dummy_s;
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
+ litedramcore_master_p3_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
dummy_d_46 = dummy_s;
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata_valid <= 1'd0;
+ litedramcore_master_p3_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
end else begin
- litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
end
// synthesis translate_off
dummy_d_47 = dummy_s;
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
+ litedramcore_master_p3_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
dummy_d_48 = dummy_s;
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
+ litedramcore_inti_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+ litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
end
// synthesis translate_off
dummy_d_49 = dummy_s;
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_address <= 14'd0;
+ litedramcore_master_p3_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
end else begin
- litedramcore_master_p1_address <= litedramcore_inti_p1_address;
+ litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
dummy_d_50 = dummy_s;
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
+ litedramcore_inti_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
dummy_d_51 = dummy_s;
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
end else begin
- litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
dummy_d_52 = dummy_s;
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
+ litedramcore_master_p3_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
+ litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
dummy_d_53 = dummy_s;
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
+ litedramcore_master_p0_address <= 14'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
end else begin
- litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
+ litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_54 = dummy_s;
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
+ litedramcore_master_p0_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
end else begin
+ litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
end
// synthesis translate_off
dummy_d_55 = dummy_s;
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
+ litedramcore_master_p0_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
+ litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_56 = dummy_s;
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
+ litedramcore_master_p0_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
dummy_d_57 = dummy_s;
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
+ litedramcore_slave_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
end else begin
- litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_58 = dummy_s;
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
+ litedramcore_master_p0_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
dummy_d_59 = dummy_s;
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
dummy_d_60 = dummy_s;
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
+ litedramcore_master_p0_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
end else begin
- litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
dummy_d_61 = dummy_s;
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
+ litedramcore_master_p0_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
end
// synthesis translate_off
dummy_d_62 = dummy_s;
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
+ litedramcore_master_p0_odt <= 1'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_63 = dummy_s;
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
+ litedramcore_master_p0_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
dummy_d_64 = dummy_s;
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
+ litedramcore_master_p0_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_65 = dummy_s;
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
+ litedramcore_master_p0_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
dummy_d_66 = dummy_s;
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
+ litedramcore_inti_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
+ litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_67 = dummy_s;
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
+ litedramcore_master_p0_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
dummy_d_68 = dummy_s;
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_address <= 14'd0;
+ litedramcore_inti_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
end else begin
- litedramcore_master_p2_address <= litedramcore_inti_p2_address;
+ litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
dummy_d_69 = dummy_s;
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
end else begin
- litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
dummy_d_70 = dummy_s;
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
+ litedramcore_master_p0_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_71 = dummy_s;
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
+ litedramcore_master_p1_address <= 14'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
end else begin
- litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_72 = dummy_s;
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
+ litedramcore_master_p1_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
end else begin
+ litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
end
// synthesis translate_off
dummy_d_73 = dummy_s;
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
+ litedramcore_master_p1_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_74 = dummy_s;
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
+ litedramcore_master_p1_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_76 = dummy_s;
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
+ litedramcore_master_p1_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
dummy_d_77 = dummy_s;
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
+ litedramcore_slave_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_78 = dummy_s;
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
+ litedramcore_master_p1_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
end else begin
- litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
+ litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
end
// synthesis translate_off
dummy_d_79 = dummy_s;
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end else begin
- litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_80 = dummy_s;
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
+ litedramcore_master_p1_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
+ litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_81 = dummy_s;
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
+ litedramcore_master_p1_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
+ litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
end
// synthesis translate_off
dummy_d_82 = dummy_s;
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata <= 32'd0;
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end else begin
- litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_83 = dummy_s;
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
+ litedramcore_master_p1_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+ litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
end
// synthesis translate_off
dummy_d_84 = dummy_s;
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata_valid <= 1'd0;
+ litedramcore_master_p1_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
end else begin
- litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
end
// synthesis translate_off
dummy_d_85 = dummy_s;
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
+ litedramcore_master_p1_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+ litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
end
// synthesis translate_off
dummy_d_86 = dummy_s;
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
+ litedramcore_inti_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
+ litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
end
// synthesis translate_off
dummy_d_87 = dummy_s;
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_address <= 14'd0;
+ litedramcore_master_p1_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_master_p3_address <= litedramcore_inti_p3_address;
+ litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
dummy_d_88 = dummy_s;
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
+ litedramcore_inti_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
+ litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
dummy_d_89 = dummy_s;
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
dummy_d_90 = dummy_s;
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
+ litedramcore_master_p1_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
+ litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_91 = dummy_s;
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
+ litedramcore_master_p2_address <= 14'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
end else begin
- litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+ litedramcore_master_p2_address <= litedramcore_inti_p2_address;
end
// synthesis translate_off
dummy_d_92 = dummy_s;
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
+ litedramcore_master_p2_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
end else begin
- litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+ litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_93 = dummy_s;
// synthesis translate_on
end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ end
+// synthesis translate_off
+ dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ end
+// synthesis translate_off
+ dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ end
+// synthesis translate_off
+ dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ end
+// synthesis translate_off
+ dummy_d_97 = dummy_s;
+// synthesis translate_on
+end
assign litedramcore_inti_p0_cke = litedramcore_storage[1];
assign litedramcore_inti_p1_cke = litedramcore_storage[1];
assign litedramcore_inti_p2_cke = litedramcore_storage[1];
assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
// synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_98;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_cas_n <= 1'd1;
litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_94 = dummy_s;
+ dummy_d_98 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_99;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_cs_n <= 1'd1;
litedramcore_inti_p0_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_95 = dummy_s;
+ dummy_d_99 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_100;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_ras_n <= 1'd1;
litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_96 = dummy_s;
+ dummy_d_100 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_97;
+reg dummy_d_101;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_we_n <= 1'd1;
litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_97 = dummy_s;
+ dummy_d_101 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_inti_p0_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_98;
+reg dummy_d_102;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_cas_n <= 1'd1;
litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_98 = dummy_s;
+ dummy_d_102 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_99;
+reg dummy_d_103;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_cs_n <= 1'd1;
litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_99 = dummy_s;
+ dummy_d_103 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_100;
+reg dummy_d_104;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_ras_n <= 1'd1;
litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_100 = dummy_s;
+ dummy_d_104 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_101;
+reg dummy_d_105;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_we_n <= 1'd1;
litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_101 = dummy_s;
+ dummy_d_105 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_inti_p1_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_102;
+reg dummy_d_106;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_cas_n <= 1'd1;
litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_102 = dummy_s;
+ dummy_d_106 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_103;
+reg dummy_d_107;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_cs_n <= 1'd1;
litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_103 = dummy_s;
+ dummy_d_107 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_104;
+reg dummy_d_108;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_ras_n <= 1'd1;
litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_104 = dummy_s;
+ dummy_d_108 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_105;
+reg dummy_d_109;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_we_n <= 1'd1;
litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_105 = dummy_s;
+ dummy_d_109 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_inti_p2_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_106;
+reg dummy_d_110;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_cas_n <= 1'd1;
litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_106 = dummy_s;
+ dummy_d_110 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_107;
+reg dummy_d_111;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_cs_n <= 1'd1;
litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_107 = dummy_s;
+ dummy_d_111 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_108;
+reg dummy_d_112;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_ras_n <= 1'd1;
litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_108 = dummy_s;
+ dummy_d_112 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_109;
+reg dummy_d_113;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_we_n <= 1'd1;
litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_109 = dummy_s;
+ dummy_d_113 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
// synthesis translate_off
-reg dummy_d_110;
+reg dummy_d_114;
// synthesis translate_on
always @(*) begin
refresher_next_state <= 2'd0;
end
endcase
// synthesis translate_off
- dummy_d_110 = dummy_s;
+ dummy_d_114 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_111;
+reg dummy_d_115;
// synthesis translate_on
always @(*) begin
litedramcore_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_111 = dummy_s;
+ dummy_d_115 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_112;
+reg dummy_d_116;
// synthesis translate_on
always @(*) begin
litedramcore_zqcs_executer_start <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_112 = dummy_s;
+ dummy_d_116 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_113;
+reg dummy_d_117;
// synthesis translate_on
always @(*) begin
litedramcore_cmd_last <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_113 = dummy_s;
+ dummy_d_117 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_114;
+reg dummy_d_118;
// synthesis translate_on
always @(*) begin
litedramcore_sequencer_start0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_114 = dummy_s;
+ dummy_d_118 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
// synthesis translate_off
-reg dummy_d_115;
+reg dummy_d_119;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_115 = dummy_s;
+ dummy_d_119 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
// synthesis translate_off
-reg dummy_d_116;
+reg dummy_d_120;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_116 = dummy_s;
+ dummy_d_120 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_117;
+reg dummy_d_121;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_117 = dummy_s;
+ dummy_d_121 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_118;
+reg dummy_d_122;
// synthesis translate_on
always @(*) begin
bankmachine0_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_118 = dummy_s;
+ dummy_d_122 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_119;
+reg dummy_d_123;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_119 = dummy_s;
+ dummy_d_123 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_120;
+reg dummy_d_124;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_124 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_125;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_120 = dummy_s;
+ dummy_d_125 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_121;
+reg dummy_d_126;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_121 = dummy_s;
+ dummy_d_126 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_122;
+reg dummy_d_127;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_122 = dummy_s;
+ dummy_d_127 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_123;
+reg dummy_d_128;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_123 = dummy_s;
+ dummy_d_128 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_129;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_124 = dummy_s;
+ dummy_d_129 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_130;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_125 = dummy_s;
+ dummy_d_130 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_131;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_126 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_127 = dummy_s;
+ dummy_d_131 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_128;
+reg dummy_d_132;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_128 = dummy_s;
+ dummy_d_132 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_129;
+reg dummy_d_133;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_129 = dummy_s;
+ dummy_d_133 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_130;
+reg dummy_d_134;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_130 = dummy_s;
+ dummy_d_134 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_131;
+reg dummy_d_135;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_131 = dummy_s;
+ dummy_d_135 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
// synthesis translate_off
-reg dummy_d_132;
+reg dummy_d_136;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_132 = dummy_s;
+ dummy_d_136 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
// synthesis translate_off
-reg dummy_d_133;
+reg dummy_d_137;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_133 = dummy_s;
+ dummy_d_137 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_134;
+reg dummy_d_138;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_134 = dummy_s;
+ dummy_d_138 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_139;
// synthesis translate_on
always @(*) begin
bankmachine1_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_135 = dummy_s;
+ dummy_d_139 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_136;
+reg dummy_d_140;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_136 = dummy_s;
+ dummy_d_140 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_137;
+reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_137 = dummy_s;
+ dummy_d_141 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_138;
+reg dummy_d_142;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_138 = dummy_s;
+ dummy_d_142 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_139;
+reg dummy_d_143;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_139 = dummy_s;
+ dummy_d_143 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_140;
+reg dummy_d_144;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_140 = dummy_s;
+ dummy_d_144 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_145;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_141 = dummy_s;
+ dummy_d_145 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_146;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_142 = dummy_s;
+ dummy_d_146 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_147;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_143 = dummy_s;
+ dummy_d_147 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_148;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_144 = dummy_s;
+ dummy_d_148 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_145;
+reg dummy_d_149;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_145 = dummy_s;
+ dummy_d_149 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_150;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_146 = dummy_s;
+ dummy_d_150 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_151;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_147 = dummy_s;
+ dummy_d_151 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_152;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_148 = dummy_s;
+ dummy_d_152 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
// synthesis translate_off
-reg dummy_d_149;
+reg dummy_d_153;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_149 = dummy_s;
+ dummy_d_153 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
// synthesis translate_off
-reg dummy_d_150;
+reg dummy_d_154;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_150 = dummy_s;
+ dummy_d_154 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_151;
+reg dummy_d_155;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_151 = dummy_s;
+ dummy_d_155 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_152;
+reg dummy_d_156;
// synthesis translate_on
always @(*) begin
bankmachine2_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_152 = dummy_s;
+ dummy_d_156 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_153;
+reg dummy_d_157;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_153 = dummy_s;
+ dummy_d_157 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_154;
+reg dummy_d_158;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_154 = dummy_s;
+ dummy_d_158 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_155;
+reg dummy_d_159;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_155 = dummy_s;
+ dummy_d_159 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_156;
+reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine2_row_open <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine2_row_open <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_156 = dummy_s;
+ dummy_d_160 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_157;
+reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
+ litedramcore_bankmachine2_row_close <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
end
3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_157 = dummy_s;
+ dummy_d_161 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_158;
+reg dummy_d_162;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_158 = dummy_s;
+ dummy_d_162 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_159;
+reg dummy_d_163;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_159 = dummy_s;
+ dummy_d_163 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_160;
+reg dummy_d_164;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_160 = dummy_s;
+ dummy_d_164 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_161;
+reg dummy_d_165;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_161 = dummy_s;
+ dummy_d_165 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_162;
+reg dummy_d_166;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_162 = dummy_s;
+ dummy_d_166 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_163;
+reg dummy_d_167;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_163 = dummy_s;
+ dummy_d_167 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_164;
+reg dummy_d_168;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_164 = dummy_s;
+ dummy_d_168 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_165;
+reg dummy_d_169;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_165 = dummy_s;
+ dummy_d_169 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
// synthesis translate_off
-reg dummy_d_166;
+reg dummy_d_170;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_166 = dummy_s;
+ dummy_d_170 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
// synthesis translate_off
-reg dummy_d_167;
+reg dummy_d_171;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_167 = dummy_s;
+ dummy_d_171 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_168;
+reg dummy_d_172;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_168 = dummy_s;
+ dummy_d_172 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_169;
+reg dummy_d_173;
// synthesis translate_on
always @(*) begin
bankmachine3_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_169 = dummy_s;
+ dummy_d_173 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_170;
+reg dummy_d_174;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_170 = dummy_s;
+ dummy_d_174 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_171;
+reg dummy_d_175;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_171 = dummy_s;
+ dummy_d_175 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_172;
+reg dummy_d_176;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_172 = dummy_s;
+ dummy_d_176 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_173;
+reg dummy_d_177;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_173 = dummy_s;
+ dummy_d_177 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_174;
+reg dummy_d_178;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_174 = dummy_s;
+ dummy_d_178 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_179;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_175 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_176;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_176 = dummy_s;
+ dummy_d_179 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_180;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_177 = dummy_s;
+ dummy_d_180 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_181;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_178 = dummy_s;
+ dummy_d_181 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_182;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_179 = dummy_s;
+ dummy_d_182 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_183;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_180 = dummy_s;
+ dummy_d_183 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_184;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_184 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_185;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_181 = dummy_s;
+ dummy_d_185 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_186;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_182 = dummy_s;
+ dummy_d_186 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
// synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_187;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_183 = dummy_s;
+ dummy_d_187 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
// synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_188;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_184 = dummy_s;
+ dummy_d_188 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_189;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_185 = dummy_s;
+ dummy_d_189 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_190;
// synthesis translate_on
always @(*) begin
bankmachine4_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_186 = dummy_s;
+ dummy_d_190 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_187;
+reg dummy_d_191;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_187 = dummy_s;
+ dummy_d_191 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_188;
+reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_188 = dummy_s;
+ dummy_d_192 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_189;
+reg dummy_d_193;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_189 = dummy_s;
+ dummy_d_193 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_190;
+reg dummy_d_194;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_194 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_195;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_190 = dummy_s;
+ dummy_d_195 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_191;
+reg dummy_d_196;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_191 = dummy_s;
+ dummy_d_196 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_192;
+reg dummy_d_197;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_192 = dummy_s;
+ dummy_d_197 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_193;
+reg dummy_d_198;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_193 = dummy_s;
+ dummy_d_198 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_194;
+reg dummy_d_199;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_194 = dummy_s;
+ dummy_d_199 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_195;
+reg dummy_d_200;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_195 = dummy_s;
+ dummy_d_200 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_196;
+reg dummy_d_201;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_196 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_197 = dummy_s;
+ dummy_d_201 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_198;
+reg dummy_d_202;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_198 = dummy_s;
+ dummy_d_202 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_199;
+reg dummy_d_203;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_199 = dummy_s;
+ dummy_d_203 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
// synthesis translate_off
-reg dummy_d_200;
+reg dummy_d_204;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_200 = dummy_s;
+ dummy_d_204 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
// synthesis translate_off
-reg dummy_d_201;
+reg dummy_d_205;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_201 = dummy_s;
+ dummy_d_205 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_202;
+reg dummy_d_206;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_202 = dummy_s;
+ dummy_d_206 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_203;
+reg dummy_d_207;
// synthesis translate_on
always @(*) begin
bankmachine5_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_203 = dummy_s;
+ dummy_d_207 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_204;
+reg dummy_d_208;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_204 = dummy_s;
+ dummy_d_208 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_205;
+reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_205 = dummy_s;
+ dummy_d_209 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_206;
+reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_206 = dummy_s;
+ dummy_d_210 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_207;
+reg dummy_d_211;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_207 = dummy_s;
+ dummy_d_211 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_208;
+reg dummy_d_212;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_208 = dummy_s;
+ dummy_d_212 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_209;
+reg dummy_d_213;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_209 = dummy_s;
+ dummy_d_213 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_210;
+reg dummy_d_214;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_210 = dummy_s;
+ dummy_d_214 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_211;
+reg dummy_d_215;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_211 = dummy_s;
+ dummy_d_215 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_212;
+reg dummy_d_216;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_212 = dummy_s;
+ dummy_d_216 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_213;
+reg dummy_d_217;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_213 = dummy_s;
+ dummy_d_217 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_218;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_214 = dummy_s;
+ dummy_d_218 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_219;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_215 = dummy_s;
+ dummy_d_219 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_220;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_216 = dummy_s;
+ dummy_d_220 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
// synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_221;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_217 = dummy_s;
+ dummy_d_221 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
// synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_222;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_218 = dummy_s;
+ dummy_d_222 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_223;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_219 = dummy_s;
+ dummy_d_223 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_220;
+reg dummy_d_224;
// synthesis translate_on
always @(*) begin
bankmachine6_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_220 = dummy_s;
+ dummy_d_224 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_221;
+reg dummy_d_225;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_221 = dummy_s;
+ dummy_d_225 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_222;
+reg dummy_d_226;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_222 = dummy_s;
+ dummy_d_226 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_223;
+reg dummy_d_227;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_223 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_224;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_224 = dummy_s;
+ dummy_d_227 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_225;
+reg dummy_d_228;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_225 = dummy_s;
+ dummy_d_228 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_226;
+reg dummy_d_229;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_226 = dummy_s;
+ dummy_d_229 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_227;
+reg dummy_d_230;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_227 = dummy_s;
+ dummy_d_230 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_231;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_228 = dummy_s;
+ dummy_d_231 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_232;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_229 = dummy_s;
+ dummy_d_232 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_233;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_230 = dummy_s;
+ dummy_d_233 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_231;
+reg dummy_d_234;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_234 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_235;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_231 = dummy_s;
+ dummy_d_235 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_232;
+reg dummy_d_236;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_232 = dummy_s;
+ dummy_d_236 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_233;
+reg dummy_d_237;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_233 = dummy_s;
+ dummy_d_237 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
// synthesis translate_off
-reg dummy_d_234;
+reg dummy_d_238;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_234 = dummy_s;
+ dummy_d_238 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
// synthesis translate_off
-reg dummy_d_235;
+reg dummy_d_239;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_235 = dummy_s;
+ dummy_d_239 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_236;
+reg dummy_d_240;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_236 = dummy_s;
+ dummy_d_240 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_237;
+reg dummy_d_241;
// synthesis translate_on
always @(*) begin
bankmachine7_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_237 = dummy_s;
+ dummy_d_241 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_238;
+reg dummy_d_242;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_242 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_243;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_238 = dummy_s;
+ dummy_d_243 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_239;
+reg dummy_d_244;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_refresh_gnt <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_239 = dummy_s;
+ dummy_d_244 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_240;
+reg dummy_d_245;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_240 = dummy_s;
+ dummy_d_245 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_241;
+reg dummy_d_246;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_open <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_241 = dummy_s;
+ dummy_d_246 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_242;
+reg dummy_d_247;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_row_close <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_242 = dummy_s;
+ dummy_d_247 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_248;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_243 = dummy_s;
+ dummy_d_248 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_249;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_244 = dummy_s;
+ dummy_d_249 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_250;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
if (litedramcore_bankmachine7_refresh_req) begin
end else begin
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-// synthesis translate_off
- dummy_d_245 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_246 = dummy_s;
+ dummy_d_250 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_247;
+reg dummy_d_251;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_247 = dummy_s;
+ dummy_d_251 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_248;
+reg dummy_d_252;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_248 = dummy_s;
+ dummy_d_252 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_249;
+reg dummy_d_253;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_249 = dummy_s;
+ dummy_d_253 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_250;
+reg dummy_d_254;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_250 = dummy_s;
+ dummy_d_254 = dummy_s;
// synthesis translate_on
end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
// synthesis translate_off
-reg dummy_d_251;
+reg dummy_d_255;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_valids <= 8'd0;
litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
// synthesis translate_off
- dummy_d_251 = dummy_s;
+ dummy_d_255 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
// synthesis translate_off
-reg dummy_d_252;
+reg dummy_d_256;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
end
// synthesis translate_off
- dummy_d_252 = dummy_s;
+ dummy_d_256 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_253;
+reg dummy_d_257;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
end
// synthesis translate_off
- dummy_d_253 = dummy_s;
+ dummy_d_257 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_254;
+reg dummy_d_258;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
end
// synthesis translate_off
- dummy_d_254 = dummy_s;
+ dummy_d_258 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_255;
+reg dummy_d_259;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_ready <= 1'd0;
litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_255 = dummy_s;
+ dummy_d_259 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_256;
+reg dummy_d_260;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_ready <= 1'd0;
litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_256 = dummy_s;
+ dummy_d_260 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_257;
+reg dummy_d_261;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_ready <= 1'd0;
litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_257 = dummy_s;
+ dummy_d_261 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_258;
+reg dummy_d_262;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_ready <= 1'd0;
litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_258 = dummy_s;
+ dummy_d_262 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_259;
+reg dummy_d_263;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_ready <= 1'd0;
litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_259 = dummy_s;
+ dummy_d_263 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_260;
+reg dummy_d_264;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_ready <= 1'd0;
litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_260 = dummy_s;
+ dummy_d_264 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_261;
+reg dummy_d_265;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_ready <= 1'd0;
litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_261 = dummy_s;
+ dummy_d_265 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_262;
+reg dummy_d_266;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_ready <= 1'd0;
litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_262 = dummy_s;
+ dummy_d_266 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
// synthesis translate_off
-reg dummy_d_263;
+reg dummy_d_267;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_valids <= 8'd0;
litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
// synthesis translate_off
- dummy_d_263 = dummy_s;
+ dummy_d_267 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
// synthesis translate_off
-reg dummy_d_264;
+reg dummy_d_268;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_cas <= 1'd0;
litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
end
// synthesis translate_off
- dummy_d_264 = dummy_s;
+ dummy_d_268 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_265;
+reg dummy_d_269;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_ras <= 1'd0;
litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
end
// synthesis translate_off
- dummy_d_265 = dummy_s;
+ dummy_d_269 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_266;
+reg dummy_d_270;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_we <= 1'd0;
litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
end
// synthesis translate_off
- dummy_d_266 = dummy_s;
+ dummy_d_270 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
// synthesis translate_off
-reg dummy_d_267;
+reg dummy_d_271;
// synthesis translate_on
always @(*) begin
multiplexer_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_267 = dummy_s;
+ dummy_d_271 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_268;
+reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
+ litedramcore_steerer_sel3 <= 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
+ litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_268 = dummy_s;
+ dummy_d_272 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_269;
+reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
+ litedramcore_en0 <= 1'd0;
case (multiplexer_state)
1'd1: begin
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_269 = dummy_s;
+ dummy_d_273 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_270;
+reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ litedramcore_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
end
2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
end
endcase
// synthesis translate_off
- dummy_d_270 = dummy_s;
+ dummy_d_274 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_271;
+reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
- dummy_d_271 = dummy_s;
+ dummy_d_275 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_272;
+reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
+ litedramcore_choose_req_want_reads <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_272 = dummy_s;
+ dummy_d_276 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_273;
+reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
+ litedramcore_choose_req_want_writes <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
+ litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
end
endcase
// synthesis translate_off
- dummy_d_273 = dummy_s;
+ dummy_d_277 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_274;
+reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
+ litedramcore_choose_req_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
endcase
// synthesis translate_off
- dummy_d_274 = dummy_s;
+ dummy_d_278 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_275;
+reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
+ litedramcore_en1 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
+ litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_275 = dummy_s;
+ dummy_d_279 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_276;
+reg dummy_d_280;
// synthesis translate_on
always @(*) begin
litedramcore_steerer_sel0 <= 2'd0;
end
endcase
// synthesis translate_off
- dummy_d_276 = dummy_s;
+ dummy_d_280 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_277;
+reg dummy_d_281;
// synthesis translate_on
always @(*) begin
litedramcore_steerer_sel1 <= 2'd0;
end
endcase
// synthesis translate_off
- dummy_d_277 = dummy_s;
+ dummy_d_281 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_278;
+reg dummy_d_282;
// synthesis translate_on
always @(*) begin
litedramcore_steerer_sel2 <= 2'd0;
end
endcase
// synthesis translate_off
- dummy_d_278 = dummy_s;
+ dummy_d_282 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_279;
+reg dummy_d_283;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_want_activates <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_279 = dummy_s;
+ dummy_d_283 = dummy_s;
// synthesis translate_on
end
assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign user_port_rdata_valid = new_master_rdata_valid8;
// synthesis translate_off
-reg dummy_d_280;
+reg dummy_d_284;
// synthesis translate_on
always @(*) begin
litedramcore_interface_wdata_we <= 16'd0;
end
endcase
// synthesis translate_off
- dummy_d_280 = dummy_s;
+ dummy_d_284 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_281;
+reg dummy_d_285;
// synthesis translate_on
always @(*) begin
litedramcore_interface_wdata <= 128'd0;
end
endcase
// synthesis translate_off
- dummy_d_281 = dummy_s;
+ dummy_d_285 = dummy_s;
// synthesis translate_on
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
// synthesis translate_off
-reg dummy_d_282;
+reg dummy_d_286;
// synthesis translate_on
always @(*) begin
csrbank0_sel <= 1'd0;
csrbank0_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_282 = dummy_s;
+ dummy_d_286 = dummy_s;
// synthesis translate_on
end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_error0_w = init_error_storage;
// synthesis translate_off
-reg dummy_d_283;
+reg dummy_d_287;
// synthesis translate_on
always @(*) begin
csrbank1_sel <= 1'd0;
csrbank1_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_283 = dummy_s;
+ dummy_d_287 = dummy_s;
// synthesis translate_on
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
// synthesis translate_off
-reg dummy_d_284;
+reg dummy_d_288;
// synthesis translate_on
always @(*) begin
csrbank2_sel <= 1'd0;
csrbank2_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_284 = dummy_s;
+ dummy_d_288 = dummy_s;
// synthesis translate_on
end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
-assign adr = csr_port_adr;
-assign we = csr_port_we;
-assign dat_w = csr_port_dat_w;
-assign csr_port_dat_r = dat_r;
+assign adr = litedramcore_adr;
+assign we = litedramcore_we;
+assign dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface2_bank_bus_adr = adr;
assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
// synthesis translate_off
-reg dummy_d_285;
+reg dummy_d_289;
// synthesis translate_on
always @(*) begin
rhs_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_285 = dummy_s;
+ dummy_d_289 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_286;
+reg dummy_d_290;
// synthesis translate_on
always @(*) begin
rhs_array_muxed1 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_286 = dummy_s;
+ dummy_d_290 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_287;
+reg dummy_d_291;
// synthesis translate_on
always @(*) begin
rhs_array_muxed2 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_287 = dummy_s;
+ dummy_d_291 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_288;
+reg dummy_d_292;
// synthesis translate_on
always @(*) begin
rhs_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_288 = dummy_s;
+ dummy_d_292 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_289;
+reg dummy_d_293;
// synthesis translate_on
always @(*) begin
rhs_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_289 = dummy_s;
+ dummy_d_293 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_294;
// synthesis translate_on
always @(*) begin
rhs_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_290 = dummy_s;
+ dummy_d_294 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_295;
// synthesis translate_on
always @(*) begin
t_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_291 = dummy_s;
+ dummy_d_295 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_296;
// synthesis translate_on
always @(*) begin
t_array_muxed1 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_292 = dummy_s;
+ dummy_d_296 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_297;
// synthesis translate_on
always @(*) begin
t_array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_293 = dummy_s;
+ dummy_d_297 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_298;
// synthesis translate_on
always @(*) begin
rhs_array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_294 = dummy_s;
+ dummy_d_298 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_299;
// synthesis translate_on
always @(*) begin
rhs_array_muxed7 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_295 = dummy_s;
+ dummy_d_299 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_300;
// synthesis translate_on
always @(*) begin
rhs_array_muxed8 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_296 = dummy_s;
+ dummy_d_300 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_301;
// synthesis translate_on
always @(*) begin
rhs_array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_297 = dummy_s;
+ dummy_d_301 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_302;
// synthesis translate_on
always @(*) begin
rhs_array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_298 = dummy_s;
+ dummy_d_302 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_299;
+reg dummy_d_303;
// synthesis translate_on
always @(*) begin
rhs_array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_299 = dummy_s;
+ dummy_d_303 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_300;
+reg dummy_d_304;
// synthesis translate_on
always @(*) begin
t_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_300 = dummy_s;
+ dummy_d_304 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_301;
+reg dummy_d_305;
// synthesis translate_on
always @(*) begin
t_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_301 = dummy_s;
+ dummy_d_305 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_302;
+reg dummy_d_306;
// synthesis translate_on
always @(*) begin
t_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_302 = dummy_s;
+ dummy_d_306 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_303;
+reg dummy_d_307;
// synthesis translate_on
always @(*) begin
rhs_array_muxed12 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_303 = dummy_s;
+ dummy_d_307 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_304;
+reg dummy_d_308;
// synthesis translate_on
always @(*) begin
rhs_array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_304 = dummy_s;
+ dummy_d_308 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_305;
+reg dummy_d_309;
// synthesis translate_on
always @(*) begin
rhs_array_muxed14 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_305 = dummy_s;
+ dummy_d_309 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_306;
+reg dummy_d_310;
// synthesis translate_on
always @(*) begin
rhs_array_muxed15 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_306 = dummy_s;
+ dummy_d_310 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_307;
+reg dummy_d_311;
// synthesis translate_on
always @(*) begin
rhs_array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_307 = dummy_s;
+ dummy_d_311 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_308;
+reg dummy_d_312;
// synthesis translate_on
always @(*) begin
rhs_array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_308 = dummy_s;
+ dummy_d_312 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_309;
+reg dummy_d_313;
// synthesis translate_on
always @(*) begin
rhs_array_muxed18 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_309 = dummy_s;
+ dummy_d_313 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_310;
+reg dummy_d_314;
// synthesis translate_on
always @(*) begin
rhs_array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_310 = dummy_s;
+ dummy_d_314 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_311;
+reg dummy_d_315;
// synthesis translate_on
always @(*) begin
rhs_array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_311 = dummy_s;
+ dummy_d_315 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_312;
+reg dummy_d_316;
// synthesis translate_on
always @(*) begin
rhs_array_muxed21 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_312 = dummy_s;
+ dummy_d_316 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_313;
+reg dummy_d_317;
// synthesis translate_on
always @(*) begin
rhs_array_muxed22 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_313 = dummy_s;
+ dummy_d_317 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_314;
+reg dummy_d_318;
// synthesis translate_on
always @(*) begin
rhs_array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_314 = dummy_s;
+ dummy_d_318 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_315;
+reg dummy_d_319;
// synthesis translate_on
always @(*) begin
rhs_array_muxed24 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_315 = dummy_s;
+ dummy_d_319 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_316;
+reg dummy_d_320;
// synthesis translate_on
always @(*) begin
rhs_array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_316 = dummy_s;
+ dummy_d_320 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_317;
+reg dummy_d_321;
// synthesis translate_on
always @(*) begin
rhs_array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_317 = dummy_s;
+ dummy_d_321 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_318;
+reg dummy_d_322;
// synthesis translate_on
always @(*) begin
rhs_array_muxed27 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_318 = dummy_s;
+ dummy_d_322 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_319;
+reg dummy_d_323;
// synthesis translate_on
always @(*) begin
rhs_array_muxed28 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_319 = dummy_s;
+ dummy_d_323 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_320;
+reg dummy_d_324;
// synthesis translate_on
always @(*) begin
rhs_array_muxed29 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_320 = dummy_s;
+ dummy_d_324 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_321;
+reg dummy_d_325;
// synthesis translate_on
always @(*) begin
rhs_array_muxed30 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_321 = dummy_s;
+ dummy_d_325 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_322;
+reg dummy_d_326;
// synthesis translate_on
always @(*) begin
rhs_array_muxed31 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_322 = dummy_s;
+ dummy_d_326 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_323;
+reg dummy_d_327;
// synthesis translate_on
always @(*) begin
rhs_array_muxed32 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_323 = dummy_s;
+ dummy_d_327 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_324;
+reg dummy_d_328;
// synthesis translate_on
always @(*) begin
rhs_array_muxed33 <= 21'd0;
end
endcase
// synthesis translate_off
- dummy_d_324 = dummy_s;
+ dummy_d_328 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_325;
+reg dummy_d_329;
// synthesis translate_on
always @(*) begin
rhs_array_muxed34 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_325 = dummy_s;
+ dummy_d_329 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_326;
+reg dummy_d_330;
// synthesis translate_on
always @(*) begin
rhs_array_muxed35 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_326 = dummy_s;
+ dummy_d_330 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_327;
+reg dummy_d_331;
// synthesis translate_on
always @(*) begin
array_muxed0 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_327 = dummy_s;
+ dummy_d_331 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_328;
+reg dummy_d_332;
// synthesis translate_on
always @(*) begin
array_muxed1 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_328 = dummy_s;
+ dummy_d_332 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_329;
+reg dummy_d_333;
// synthesis translate_on
always @(*) begin
array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_329 = dummy_s;
+ dummy_d_333 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_330;
+reg dummy_d_334;
// synthesis translate_on
always @(*) begin
array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_330 = dummy_s;
+ dummy_d_334 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_331;
+reg dummy_d_335;
// synthesis translate_on
always @(*) begin
array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_331 = dummy_s;
+ dummy_d_335 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_332;
+reg dummy_d_336;
// synthesis translate_on
always @(*) begin
array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_332 = dummy_s;
+ dummy_d_336 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_333;
+reg dummy_d_337;
// synthesis translate_on
always @(*) begin
array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_333 = dummy_s;
+ dummy_d_337 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_334;
+reg dummy_d_338;
// synthesis translate_on
always @(*) begin
array_muxed7 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_334 = dummy_s;
+ dummy_d_338 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_335;
+reg dummy_d_339;
// synthesis translate_on
always @(*) begin
array_muxed8 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_335 = dummy_s;
+ dummy_d_339 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_336;
+reg dummy_d_340;
// synthesis translate_on
always @(*) begin
array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_336 = dummy_s;
+ dummy_d_340 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_337;
+reg dummy_d_341;
// synthesis translate_on
always @(*) begin
array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_337 = dummy_s;
+ dummy_d_341 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_342;
// synthesis translate_on
always @(*) begin
array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_338 = dummy_s;
+ dummy_d_342 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_343;
// synthesis translate_on
always @(*) begin
array_muxed12 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_339 = dummy_s;
+ dummy_d_343 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_344;
// synthesis translate_on
always @(*) begin
array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_340 = dummy_s;
+ dummy_d_344 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_345;
// synthesis translate_on
always @(*) begin
array_muxed14 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_341 = dummy_s;
+ dummy_d_345 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_346;
// synthesis translate_on
always @(*) begin
array_muxed15 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_342 = dummy_s;
+ dummy_d_346 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_347;
// synthesis translate_on
always @(*) begin
array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_343 = dummy_s;
+ dummy_d_347 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_348;
// synthesis translate_on
always @(*) begin
array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_344 = dummy_s;
+ dummy_d_348 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_349;
// synthesis translate_on
always @(*) begin
array_muxed18 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_345 = dummy_s;
+ dummy_d_349 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_350;
// synthesis translate_on
always @(*) begin
array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_346 = dummy_s;
+ dummy_d_350 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_351;
// synthesis translate_on
always @(*) begin
array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_347 = dummy_s;
+ dummy_d_351 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_352;
// synthesis translate_on
always @(*) begin
array_muxed21 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_348 = dummy_s;
+ dummy_d_352 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_353;
// synthesis translate_on
always @(*) begin
array_muxed22 <= 14'd0;
end
endcase
// synthesis translate_off
- dummy_d_349 = dummy_s;
+ dummy_d_353 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_354;
// synthesis translate_on
always @(*) begin
array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_350 = dummy_s;
+ dummy_d_354 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_355;
// synthesis translate_on
always @(*) begin
array_muxed24 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_351 = dummy_s;
+ dummy_d_355 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_356;
// synthesis translate_on
always @(*) begin
array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_352 = dummy_s;
+ dummy_d_356 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_357;
// synthesis translate_on
always @(*) begin
array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_353 = dummy_s;
+ dummy_d_357 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_358;
// synthesis translate_on
always @(*) begin
array_muxed27 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_354 = dummy_s;
+ dummy_d_358 = dummy_s;
// synthesis translate_on
end
assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
end
always @(posedge sys_clk) begin
+ state <= next_state;
a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip0_value <= 1'd0;
end
- a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]};
+ a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip1_value <= 1'd0;
end
- a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]};
+ a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip2_value <= 1'd0;
end
- a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]};
+ a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip3_value <= 1'd0;
end
- a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]};
+ a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip4_value <= 1'd0;
end
- a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]};
+ a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip5_value <= 1'd0;
end
- a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]};
+ a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip6_value <= 1'd0;
end
- a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]};
+ a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip7_value <= 1'd0;
end
- a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]};
+ a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip8_value <= 1'd0;
end
- a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]};
+ a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip9_value <= 1'd0;
end
- a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]};
+ a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip10_value <= 1'd0;
end
- a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]};
+ a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip11_value <= 1'd0;
end
- a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]};
+ a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip12_value <= 1'd0;
end
- a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]};
+ a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip13_value <= 1'd0;
end
- a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]};
+ a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip14_value <= 1'd0;
end
- a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]};
+ a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip15_value <= 1'd0;
end
- a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]};
+ a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]};
if (litedramcore_inti_p0_rddata_valid) begin
litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
end
a7ddrphy_dqs_oe_delayed <= 1'd0;
a7ddrphy_dqspattern_o1 <= 8'd0;
a7ddrphy_dq_oe_delayed <= 1'd0;
- a7ddrphy_bitslip0_value <= 3'd0;
- a7ddrphy_bitslip1_value <= 3'd0;
- a7ddrphy_bitslip2_value <= 3'd0;
- a7ddrphy_bitslip3_value <= 3'd0;
- a7ddrphy_bitslip4_value <= 3'd0;
- a7ddrphy_bitslip5_value <= 3'd0;
- a7ddrphy_bitslip6_value <= 3'd0;
- a7ddrphy_bitslip7_value <= 3'd0;
- a7ddrphy_bitslip8_value <= 3'd0;
- a7ddrphy_bitslip9_value <= 3'd0;
- a7ddrphy_bitslip10_value <= 3'd0;
- a7ddrphy_bitslip11_value <= 3'd0;
- a7ddrphy_bitslip12_value <= 3'd0;
- a7ddrphy_bitslip13_value <= 3'd0;
- a7ddrphy_bitslip14_value <= 3'd0;
- a7ddrphy_bitslip15_value <= 3'd0;
+ a7ddrphy_bitslip0_value <= 4'd0;
+ a7ddrphy_bitslip1_value <= 4'd0;
+ a7ddrphy_bitslip2_value <= 4'd0;
+ a7ddrphy_bitslip3_value <= 4'd0;
+ a7ddrphy_bitslip4_value <= 4'd0;
+ a7ddrphy_bitslip5_value <= 4'd0;
+ a7ddrphy_bitslip6_value <= 4'd0;
+ a7ddrphy_bitslip7_value <= 4'd0;
+ a7ddrphy_bitslip8_value <= 4'd0;
+ a7ddrphy_bitslip9_value <= 4'd0;
+ a7ddrphy_bitslip10_value <= 4'd0;
+ a7ddrphy_bitslip11_value <= 4'd0;
+ a7ddrphy_bitslip12_value <= 4'd0;
+ a7ddrphy_bitslip13_value <= 4'd0;
+ a7ddrphy_bitslip14_value <= 4'd0;
+ a7ddrphy_bitslip15_value <= 4'd0;
a7ddrphy_rddata_en_last <= 8'd0;
a7ddrphy_wrdata_en_last <= 4'd0;
litedramcore_storage <= 4'd0;
init_done_re <= 1'd0;
init_error_storage <= 1'd0;
init_error_re <= 1'd0;
+ state <= 1'd0;
refresher_state <= 2'd0;
bankmachine0_state <= 4'd0;
bankmachine1_state <= 4'd0;
//--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 11:57:13
+// Auto-generated by Migen (0d16e03) & LiteX (3391398a) on 2020-05-15 09:40:28
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
output wire ddram_reset_n,
output wire init_done,
output wire init_error,
- input wire [13:0] csr_port0_adr,
- input wire csr_port0_we,
- input wire [31:0] csr_port0_dat_w,
- output wire [31:0] csr_port0_dat_r,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
output wire user_clk,
output wire user_rst,
input wire user_port_native_0_cmd_valid,
output wire [127:0] user_port_native_0_rdata_data
);
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+wire [31:0] litedramcore_dat_w;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+wire [31:0] litedramcore_wishbone_dat_r;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
wire sys_clk;
wire sys_rst;
wire sys4x_clk;
wire [7:0] a7ddrphy_dq_i_data0;
wire [7:0] a7ddrphy_bitslip0_i;
reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip0_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip0_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip0_r = 24'd0;
wire a7ddrphy_dq_o_nodelay1;
wire a7ddrphy_dq_i_nodelay1;
wire a7ddrphy_dq_i_delayed1;
wire [7:0] a7ddrphy_dq_i_data1;
wire [7:0] a7ddrphy_bitslip1_i;
reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip1_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip1_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip1_r = 24'd0;
wire a7ddrphy_dq_o_nodelay2;
wire a7ddrphy_dq_i_nodelay2;
wire a7ddrphy_dq_i_delayed2;
wire [7:0] a7ddrphy_dq_i_data2;
wire [7:0] a7ddrphy_bitslip2_i;
reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip2_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip2_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip2_r = 24'd0;
wire a7ddrphy_dq_o_nodelay3;
wire a7ddrphy_dq_i_nodelay3;
wire a7ddrphy_dq_i_delayed3;
wire [7:0] a7ddrphy_dq_i_data3;
wire [7:0] a7ddrphy_bitslip3_i;
reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip3_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip3_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip3_r = 24'd0;
wire a7ddrphy_dq_o_nodelay4;
wire a7ddrphy_dq_i_nodelay4;
wire a7ddrphy_dq_i_delayed4;
wire [7:0] a7ddrphy_dq_i_data4;
wire [7:0] a7ddrphy_bitslip4_i;
reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip4_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip4_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip4_r = 24'd0;
wire a7ddrphy_dq_o_nodelay5;
wire a7ddrphy_dq_i_nodelay5;
wire a7ddrphy_dq_i_delayed5;
wire [7:0] a7ddrphy_dq_i_data5;
wire [7:0] a7ddrphy_bitslip5_i;
reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip5_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip5_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip5_r = 24'd0;
wire a7ddrphy_dq_o_nodelay6;
wire a7ddrphy_dq_i_nodelay6;
wire a7ddrphy_dq_i_delayed6;
wire [7:0] a7ddrphy_dq_i_data6;
wire [7:0] a7ddrphy_bitslip6_i;
reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip6_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip6_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip6_r = 24'd0;
wire a7ddrphy_dq_o_nodelay7;
wire a7ddrphy_dq_i_nodelay7;
wire a7ddrphy_dq_i_delayed7;
wire [7:0] a7ddrphy_dq_i_data7;
wire [7:0] a7ddrphy_bitslip7_i;
reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip7_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip7_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip7_r = 24'd0;
wire a7ddrphy_dq_o_nodelay8;
wire a7ddrphy_dq_i_nodelay8;
wire a7ddrphy_dq_i_delayed8;
wire [7:0] a7ddrphy_dq_i_data8;
wire [7:0] a7ddrphy_bitslip8_i;
reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip8_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip8_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip8_r = 24'd0;
wire a7ddrphy_dq_o_nodelay9;
wire a7ddrphy_dq_i_nodelay9;
wire a7ddrphy_dq_i_delayed9;
wire [7:0] a7ddrphy_dq_i_data9;
wire [7:0] a7ddrphy_bitslip9_i;
reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip9_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip9_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip9_r = 24'd0;
wire a7ddrphy_dq_o_nodelay10;
wire a7ddrphy_dq_i_nodelay10;
wire a7ddrphy_dq_i_delayed10;
wire [7:0] a7ddrphy_dq_i_data10;
wire [7:0] a7ddrphy_bitslip10_i;
reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip10_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip10_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip10_r = 24'd0;
wire a7ddrphy_dq_o_nodelay11;
wire a7ddrphy_dq_i_nodelay11;
wire a7ddrphy_dq_i_delayed11;
wire [7:0] a7ddrphy_dq_i_data11;
wire [7:0] a7ddrphy_bitslip11_i;
reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip11_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip11_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip11_r = 24'd0;
wire a7ddrphy_dq_o_nodelay12;
wire a7ddrphy_dq_i_nodelay12;
wire a7ddrphy_dq_i_delayed12;
wire [7:0] a7ddrphy_dq_i_data12;
wire [7:0] a7ddrphy_bitslip12_i;
reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip12_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip12_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip12_r = 24'd0;
wire a7ddrphy_dq_o_nodelay13;
wire a7ddrphy_dq_i_nodelay13;
wire a7ddrphy_dq_i_delayed13;
wire [7:0] a7ddrphy_dq_i_data13;
wire [7:0] a7ddrphy_bitslip13_i;
reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip13_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip13_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip13_r = 24'd0;
wire a7ddrphy_dq_o_nodelay14;
wire a7ddrphy_dq_i_nodelay14;
wire a7ddrphy_dq_i_delayed14;
wire [7:0] a7ddrphy_dq_i_data14;
wire [7:0] a7ddrphy_bitslip14_i;
reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip14_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip14_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip14_r = 24'd0;
wire a7ddrphy_dq_o_nodelay15;
wire a7ddrphy_dq_i_nodelay15;
wire a7ddrphy_dq_i_delayed15;
wire [7:0] a7ddrphy_dq_i_data15;
wire [7:0] a7ddrphy_bitslip15_i;
reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value = 3'd0;
-reg [15:0] a7ddrphy_bitslip15_r = 16'd0;
+reg [3:0] a7ddrphy_bitslip15_value = 4'd0;
+reg [23:0] a7ddrphy_bitslip15_r = 24'd0;
wire [7:0] a7ddrphy_rddata_en;
reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
wire [3:0] a7ddrphy_wrdata_en;
reg init_done_re = 1'd0;
reg init_error_storage = 1'd0;
reg init_error_re = 1'd0;
-wire [13:0] csr_port_adr;
-wire csr_port_we;
-wire [31:0] csr_port_dat_w;
-wire [31:0] csr_port_dat_r;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
wire user_port_cmd_valid;
wire user_port_cmd_ready;
wire user_port_cmd_payload_we;
wire user_port_rdata_valid;
wire user_port_rdata_ready;
wire [127:0] user_port_rdata_payload_data;
+reg state = 1'd0;
+reg next_state = 1'd0;
wire pll_fb0;
wire pll_fb1;
reg [1:0] refresher_state = 2'd0;
// synthesis translate_on
assign init_done = init_done_storage;
assign init_error = init_error_storage;
-assign csr_port_adr = csr_port0_adr;
-assign csr_port_we = csr_port0_we;
-assign csr_port_dat_w = csr_port0_dat_w;
-assign csr_port0_dat_r = csr_port_dat_r;
+assign wb_bus_adr = wb_ctrl_adr;
+assign wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wb_ctrl_sel;
+assign wb_bus_cyc = wb_ctrl_cyc;
+assign wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = wb_bus_ack;
+assign wb_bus_we = wb_ctrl_we;
+assign wb_bus_cti = wb_ctrl_cti;
+assign wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = wb_bus_err;
assign user_clk = sys_clk;
assign user_rst = sys_rst;
assign user_port_cmd_valid = user_port_native_0_cmd_valid;
assign user_port_native_0_rdata_valid = user_port_rdata_valid;
assign user_port_rdata_ready = user_port_native_0_rdata_ready;
assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign litedramcore_dat_w = litedramcore_wishbone_dat_w;
+assign litedramcore_wishbone_dat_r = litedramcore_dat_r;
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+ next_state <= 1'd0;
+ next_state <= state;
+ case (state)
+ 1'd1: begin
+ next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ next_state <= 1'd1;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_adr <= 14'd0;
+ case (state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_1 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_we <= 1'd0;
+ case (state)
+ 1'd1: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we <= litedramcore_wishbone_we;
+ end
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_2 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (state)
+ 1'd1: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_3 = dummy_s;
+// synthesis translate_on
+end
assign sys_pll_reset = rst;
assign pll_locked = sys_pll_locked;
assign iodelay_pll_reset = rst;
assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
// synthesis translate_off
-reg dummy_d;
+reg dummy_d_4;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p0_rddata <= 32'd0;
a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
// synthesis translate_off
- dummy_d = dummy_s;
+ dummy_d_4 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_1;
+reg dummy_d_5;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p1_rddata <= 32'd0;
a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
// synthesis translate_off
- dummy_d_1 = dummy_s;
+ dummy_d_5 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_2;
+reg dummy_d_6;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p2_rddata <= 32'd0;
a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
// synthesis translate_off
- dummy_d_2 = dummy_s;
+ dummy_d_6 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_3;
+reg dummy_d_7;
// synthesis translate_on
always @(*) begin
a7ddrphy_dfi_p3_rddata <= 32'd0;
a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
// synthesis translate_off
- dummy_d_3 = dummy_s;
+ dummy_d_7 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
// synthesis translate_off
-reg dummy_d_4;
+reg dummy_d_8;
// synthesis translate_on
always @(*) begin
a7ddrphy_dqs_oe <= 1'd0;
a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
end
// synthesis translate_off
- dummy_d_4 = dummy_s;
+ dummy_d_8 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
// synthesis translate_off
-reg dummy_d_5;
+reg dummy_d_9;
// synthesis translate_on
always @(*) begin
a7ddrphy_dqspattern_o0 <= 8'd0;
end
end
// synthesis translate_off
- dummy_d_5 = dummy_s;
+ dummy_d_9 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_6;
+reg dummy_d_10;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip0_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_6 = dummy_s;
+ dummy_d_10 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_7;
+reg dummy_d_11;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip1_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_7 = dummy_s;
+ dummy_d_11 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_8;
+reg dummy_d_12;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip2_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_8 = dummy_s;
+ dummy_d_12 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_9;
+reg dummy_d_13;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip3_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_9 = dummy_s;
+ dummy_d_13 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_10;
+reg dummy_d_14;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip4_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_10 = dummy_s;
+ dummy_d_14 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_11;
+reg dummy_d_15;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip5_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_11 = dummy_s;
+ dummy_d_15 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_12;
+reg dummy_d_16;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip6_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_12 = dummy_s;
+ dummy_d_16 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_13;
+reg dummy_d_17;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip7_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_13 = dummy_s;
+ dummy_d_17 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_14;
+reg dummy_d_18;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip8_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_14 = dummy_s;
+ dummy_d_18 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_15;
+reg dummy_d_19;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip9_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_15 = dummy_s;
+ dummy_d_19 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_16;
+reg dummy_d_20;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip10_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_16 = dummy_s;
+ dummy_d_20 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_17;
+reg dummy_d_21;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip11_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
end
- endcase
-// synthesis translate_off
- dummy_d_17 = dummy_s;
-// synthesis translate_on
-end
-
+ 4'd8: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[22:15];
+ end
+ endcase
// synthesis translate_off
-reg dummy_d_18;
+ dummy_d_21 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_22;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip12_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_18 = dummy_s;
+ dummy_d_22 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_19;
+reg dummy_d_23;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip13_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_19 = dummy_s;
+ dummy_d_23 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_20;
+reg dummy_d_24;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip14_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_20 = dummy_s;
+ dummy_d_24 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_21;
+reg dummy_d_25;
// synthesis translate_on
always @(*) begin
a7ddrphy_bitslip15_o <= 8'd0;
3'd7: begin
a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
end
+ 4'd8: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[15:8];
+ end
+ 4'd9: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[16:9];
+ end
+ 4'd10: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[17:10];
+ end
+ 4'd11: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[18:11];
+ end
+ 4'd12: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[19:12];
+ end
+ 4'd13: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[20:13];
+ end
+ 4'd14: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[21:14];
+ end
+ 4'd15: begin
+ a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[22:15];
+ end
endcase
// synthesis translate_off
- dummy_d_21 = dummy_s;
+ dummy_d_25 = dummy_s;
// synthesis translate_on
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
-// synthesis translate_off
-reg dummy_d_22;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
- end
-// synthesis translate_off
- dummy_d_22 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_23;
-// synthesis translate_on
-always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
-// synthesis translate_off
- dummy_d_23 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_24;
-// synthesis translate_on
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_storage[0]) begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
- end
-// synthesis translate_off
- dummy_d_24 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_25;
-// synthesis translate_on
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_storage[0]) begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
-// synthesis translate_off
- dummy_d_25 = dummy_s;
-// synthesis translate_on
-end
-
// synthesis translate_off
reg dummy_d_26;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
+ litedramcore_master_p1_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
end else begin
- litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
+ litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
end
// synthesis translate_off
dummy_d_26 = dummy_s;
reg dummy_d_27;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
+ litedramcore_inti_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
end else begin
- litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end
// synthesis translate_off
dummy_d_27 = dummy_s;
reg dummy_d_28;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
end else begin
- litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
end
// synthesis translate_off
dummy_d_28 = dummy_s;
reg dummy_d_29;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
+ litedramcore_master_p1_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
end else begin
- litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_29 = dummy_s;
reg dummy_d_30;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
+ litedramcore_master_p2_address <= 15'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
end else begin
- litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ litedramcore_master_p2_address <= litedramcore_inti_p2_address;
end
// synthesis translate_off
dummy_d_30 = dummy_s;
reg dummy_d_31;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata <= 32'd0;
+ litedramcore_master_p2_bank <= 3'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
end else begin
- litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
+ litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_31 = dummy_s;
reg dummy_d_32;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
+ litedramcore_master_p2_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
+ litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
end
// synthesis translate_off
dummy_d_32 = dummy_s;
reg dummy_d_33;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_rddata_valid <= 1'd0;
+ litedramcore_master_p2_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
end
// synthesis translate_off
dummy_d_33 = dummy_s;
reg dummy_d_34;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
+ litedramcore_master_p2_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
+ litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
end
// synthesis translate_off
dummy_d_34 = dummy_s;
reg dummy_d_35;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
+ litedramcore_slave_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
end
// synthesis translate_off
dummy_d_35 = dummy_s;
reg dummy_d_36;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_address <= 15'd0;
+ litedramcore_master_p2_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
end else begin
- litedramcore_master_p2_address <= litedramcore_inti_p2_address;
+ litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
end
// synthesis translate_off
dummy_d_36 = dummy_s;
reg dummy_d_37;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
end else begin
- litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
end
// synthesis translate_off
dummy_d_37 = dummy_s;
reg dummy_d_38;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
+ litedramcore_master_p2_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
+ litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
end
// synthesis translate_off
dummy_d_38 = dummy_s;
reg dummy_d_39;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
+ litedramcore_inti_p2_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
end else begin
- litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
+ litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
end
// synthesis translate_off
dummy_d_39 = dummy_s;
reg dummy_d_40;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
+ litedramcore_master_p2_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
end else begin
- litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
+ litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
end
// synthesis translate_off
dummy_d_40 = dummy_s;
reg dummy_d_41;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
+ litedramcore_master_p2_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
end
// synthesis translate_off
dummy_d_41 = dummy_s;
reg dummy_d_42;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
+ litedramcore_master_p2_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
end else begin
- litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
+ litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
end
// synthesis translate_off
dummy_d_42 = dummy_s;
reg dummy_d_43;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
+ litedramcore_master_p2_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
end
// synthesis translate_off
dummy_d_43 = dummy_s;
reg dummy_d_44;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
+ litedramcore_inti_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
end else begin
- litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
+ litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
end
// synthesis translate_off
dummy_d_44 = dummy_s;
reg dummy_d_45;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
+ litedramcore_master_p2_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
end else begin
- litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
+ litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
end
// synthesis translate_off
dummy_d_45 = dummy_s;
reg dummy_d_46;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
+ litedramcore_inti_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
end else begin
- litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
+ litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end
// synthesis translate_off
dummy_d_46 = dummy_s;
reg dummy_d_47;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
end else begin
- litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
+ litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
end
// synthesis translate_off
dummy_d_47 = dummy_s;
reg dummy_d_48;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
+ litedramcore_master_p2_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
end else begin
- litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
+ litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
end
// synthesis translate_off
dummy_d_48 = dummy_s;
reg dummy_d_49;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata <= 32'd0;
+ litedramcore_master_p3_address <= 15'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
end else begin
- litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
+ litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_49 = dummy_s;
reg dummy_d_50;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
+ litedramcore_master_p3_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+ litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
end
// synthesis translate_off
dummy_d_50 = dummy_s;
reg dummy_d_51;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p3_rddata_valid <= 1'd0;
+ litedramcore_master_p3_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
end else begin
- litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_51 = dummy_s;
reg dummy_d_52;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
+ litedramcore_master_p3_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+ litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
end
// synthesis translate_off
dummy_d_52 = dummy_s;
reg dummy_d_53;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
+ litedramcore_master_p3_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
+ litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
end
// synthesis translate_off
dummy_d_53 = dummy_s;
reg dummy_d_54;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_address <= 15'd0;
+ litedramcore_slave_p3_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
end else begin
- litedramcore_master_p3_address <= litedramcore_inti_p3_address;
end
// synthesis translate_off
dummy_d_54 = dummy_s;
reg dummy_d_55;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
+ litedramcore_master_p3_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
end else begin
- litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
+ litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
end
// synthesis translate_off
dummy_d_55 = dummy_s;
reg dummy_d_56;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
end else begin
- litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
end
// synthesis translate_off
dummy_d_56 = dummy_s;
reg dummy_d_57;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
+ litedramcore_master_p3_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
+ litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
end
// synthesis translate_off
dummy_d_57 = dummy_s;
reg dummy_d_58;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
+ litedramcore_master_p3_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
end else begin
- litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+ litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
end
// synthesis translate_off
dummy_d_58 = dummy_s;
reg dummy_d_59;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
+ litedramcore_master_p3_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
end
// synthesis translate_off
dummy_d_59 = dummy_s;
reg dummy_d_60;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
+ litedramcore_master_p3_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
end else begin
- litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+ litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
end
// synthesis translate_off
dummy_d_60 = dummy_s;
reg dummy_d_61;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
+ litedramcore_master_p3_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
end
// synthesis translate_off
dummy_d_61 = dummy_s;
reg dummy_d_62;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
+ litedramcore_inti_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
end else begin
- litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
+ litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
end
// synthesis translate_off
dummy_d_62 = dummy_s;
reg dummy_d_63;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
+ litedramcore_master_p3_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
end else begin
- litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
+ litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
end
// synthesis translate_off
dummy_d_63 = dummy_s;
reg dummy_d_64;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
+ litedramcore_inti_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
end else begin
- litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
+ litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end
// synthesis translate_off
dummy_d_64 = dummy_s;
reg dummy_d_65;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
end else begin
- litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
+ litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
end
// synthesis translate_off
dummy_d_65 = dummy_s;
reg dummy_d_66;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
+ litedramcore_master_p3_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
end else begin
- litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
+ litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
end
// synthesis translate_off
dummy_d_66 = dummy_s;
reg dummy_d_67;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata <= 32'd0;
+ litedramcore_master_p0_address <= 15'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
end else begin
- litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_67 = dummy_s;
reg dummy_d_68;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
+ litedramcore_master_p0_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
+ litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
end
// synthesis translate_off
dummy_d_68 = dummy_s;
reg dummy_d_69;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_rddata_valid <= 1'd0;
+ litedramcore_master_p0_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
end else begin
- litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_69 = dummy_s;
reg dummy_d_70;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
+ litedramcore_master_p0_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
+ litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
end
// synthesis translate_off
dummy_d_70 = dummy_s;
reg dummy_d_71;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
+ litedramcore_master_p0_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
+ litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
end
// synthesis translate_off
dummy_d_71 = dummy_s;
reg dummy_d_72;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
+ litedramcore_slave_p0_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
end else begin
- litedramcore_master_p0_address <= litedramcore_inti_p0_address;
end
// synthesis translate_off
dummy_d_72 = dummy_s;
reg dummy_d_73;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
+ litedramcore_master_p0_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
end else begin
- litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+ litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
end
// synthesis translate_off
dummy_d_73 = dummy_s;
reg dummy_d_74;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
end else begin
- litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
end
// synthesis translate_off
dummy_d_74 = dummy_s;
reg dummy_d_75;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
+ litedramcore_master_p0_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+ litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
end
// synthesis translate_off
dummy_d_75 = dummy_s;
reg dummy_d_76;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
+ litedramcore_master_p0_odt <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
end else begin
- litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+ litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
end
// synthesis translate_off
dummy_d_76 = dummy_s;
reg dummy_d_77;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
+ litedramcore_master_p0_reset_n <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
end
// synthesis translate_off
dummy_d_77 = dummy_s;
reg dummy_d_78;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
+ litedramcore_master_p0_act_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
end else begin
- litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+ litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
end
// synthesis translate_off
dummy_d_78 = dummy_s;
reg dummy_d_79;
// synthesis translate_on
always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
+ litedramcore_master_p0_wrdata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
end
// synthesis translate_off
dummy_d_79 = dummy_s;
reg dummy_d_80;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
+ litedramcore_inti_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
end else begin
- litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+ litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
end
// synthesis translate_off
dummy_d_80 = dummy_s;
reg dummy_d_81;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
+ litedramcore_master_p0_wrdata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
end else begin
- litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+ litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
end
// synthesis translate_off
dummy_d_81 = dummy_s;
reg dummy_d_82;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
+ litedramcore_inti_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
end else begin
- litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+ litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end
// synthesis translate_off
dummy_d_82 = dummy_s;
reg dummy_d_83;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
end else begin
- litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+ litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
end
// synthesis translate_off
dummy_d_83 = dummy_s;
reg dummy_d_84;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
+ litedramcore_master_p0_rddata_en <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
end else begin
- litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+ litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
end
// synthesis translate_off
dummy_d_84 = dummy_s;
reg dummy_d_85;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata <= 32'd0;
+ litedramcore_master_p1_address <= 15'd0;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
end else begin
- litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
+ litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_85 = dummy_s;
reg dummy_d_86;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
+ litedramcore_master_p1_bank <= 3'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
+ litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
end
// synthesis translate_off
dummy_d_86 = dummy_s;
reg dummy_d_87;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_rddata_valid <= 1'd0;
+ litedramcore_master_p1_cas_n <= 1'd1;
if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
end else begin
- litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_87 = dummy_s;
reg dummy_d_88;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
+ litedramcore_master_p1_cs_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
+ litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
end
// synthesis translate_off
dummy_d_88 = dummy_s;
reg dummy_d_89;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
+ litedramcore_master_p1_ras_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
+ litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
end
// synthesis translate_off
dummy_d_89 = dummy_s;
reg dummy_d_90;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
+ litedramcore_slave_p1_rddata <= 32'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
end else begin
- litedramcore_master_p1_address <= litedramcore_inti_p1_address;
end
// synthesis translate_off
dummy_d_90 = dummy_s;
reg dummy_d_91;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
+ litedramcore_master_p1_we_n <= 1'd1;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
end else begin
- litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
+ litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
end
// synthesis translate_off
dummy_d_91 = dummy_s;
reg dummy_d_92;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
end else begin
- litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
end
// synthesis translate_off
dummy_d_92 = dummy_s;
reg dummy_d_93;
// synthesis translate_on
always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
+ litedramcore_master_p1_cke <= 1'd0;
if (litedramcore_storage[0]) begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
end else begin
- litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
+ litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
end
// synthesis translate_off
dummy_d_93 = dummy_s;
// synthesis translate_on
end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
+ end
+// synthesis translate_off
+ dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
+ end
+// synthesis translate_off
+ dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
+ end
+// synthesis translate_off
+ dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 32'd0;
+ if (litedramcore_storage[0]) begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
+ end
+// synthesis translate_off
+ dummy_d_97 = dummy_s;
+// synthesis translate_on
+end
assign litedramcore_inti_p0_cke = litedramcore_storage[1];
assign litedramcore_inti_p1_cke = litedramcore_storage[1];
assign litedramcore_inti_p2_cke = litedramcore_storage[1];
assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
// synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_98;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_inti_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ end else begin
+ litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ end
+// synthesis translate_off
+ dummy_d_98 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_99;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_ras_n <= 1'd1;
litedramcore_inti_p0_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_94 = dummy_s;
+ dummy_d_99 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_100;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_we_n <= 1'd1;
litedramcore_inti_p0_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_95 = dummy_s;
+ dummy_d_100 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_101;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p0_cas_n <= 1'd1;
litedramcore_inti_p0_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_96 = dummy_s;
+ dummy_d_101 = dummy_s;
// synthesis translate_on
end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_97;
+reg dummy_d_102;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
+ litedramcore_inti_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
end else begin
- litedramcore_inti_p0_cs_n <= {1{1'd1}};
+ litedramcore_inti_p1_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_97 = dummy_s;
+ dummy_d_102 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
-assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
-assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
-assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
-assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
-assign litedramcore_inti_p0_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_98;
+reg dummy_d_103;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_ras_n <= 1'd1;
litedramcore_inti_p1_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_98 = dummy_s;
+ dummy_d_103 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_99;
+reg dummy_d_104;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_we_n <= 1'd1;
litedramcore_inti_p1_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_99 = dummy_s;
+ dummy_d_104 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_100;
+reg dummy_d_105;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p1_cas_n <= 1'd1;
litedramcore_inti_p1_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_100 = dummy_s;
+ dummy_d_105 = dummy_s;
// synthesis translate_on
end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_101;
+reg dummy_d_106;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
+ litedramcore_inti_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
end else begin
- litedramcore_inti_p1_cs_n <= {1{1'd1}};
+ litedramcore_inti_p2_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_101 = dummy_s;
+ dummy_d_106 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
-assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
-assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
-assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
-assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
-assign litedramcore_inti_p1_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_102;
+reg dummy_d_107;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_ras_n <= 1'd1;
litedramcore_inti_p2_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_102 = dummy_s;
+ dummy_d_107 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_103;
+reg dummy_d_108;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_we_n <= 1'd1;
litedramcore_inti_p2_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_103 = dummy_s;
+ dummy_d_108 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_104;
+reg dummy_d_109;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p2_cas_n <= 1'd1;
litedramcore_inti_p2_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_104 = dummy_s;
+ dummy_d_109 = dummy_s;
// synthesis translate_on
end
+assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
+assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
+assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_inti_p2_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_105;
+reg dummy_d_110;
// synthesis translate_on
always @(*) begin
- litedramcore_inti_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
+ litedramcore_inti_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
end else begin
- litedramcore_inti_p2_cs_n <= {1{1'd1}};
+ litedramcore_inti_p3_cs_n <= {1{1'd1}};
end
// synthesis translate_off
- dummy_d_105 = dummy_s;
+ dummy_d_110 = dummy_s;
// synthesis translate_on
end
-assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
-assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
-assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
-assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
-assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
-assign litedramcore_inti_p2_wrdata_mask = 1'd0;
// synthesis translate_off
-reg dummy_d_106;
+reg dummy_d_111;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_ras_n <= 1'd1;
litedramcore_inti_p3_ras_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_106 = dummy_s;
+ dummy_d_111 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_107;
+reg dummy_d_112;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_we_n <= 1'd1;
litedramcore_inti_p3_we_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_107 = dummy_s;
+ dummy_d_112 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_108;
+reg dummy_d_113;
// synthesis translate_on
always @(*) begin
litedramcore_inti_p3_cas_n <= 1'd1;
litedramcore_inti_p3_cas_n <= 1'd1;
end
// synthesis translate_off
- dummy_d_108 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_109;
-// synthesis translate_on
-always @(*) begin
- litedramcore_inti_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
- end else begin
- litedramcore_inti_p3_cs_n <= {1{1'd1}};
- end
-// synthesis translate_off
- dummy_d_109 = dummy_s;
+ dummy_d_113 = dummy_s;
// synthesis translate_on
end
assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
// synthesis translate_off
-reg dummy_d_110;
+reg dummy_d_114;
// synthesis translate_on
always @(*) begin
refresher_next_state <= 2'd0;
end
endcase
// synthesis translate_off
- dummy_d_110 = dummy_s;
+ dummy_d_114 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_111;
+reg dummy_d_115;
+// synthesis translate_on
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+// synthesis translate_off
+ dummy_d_115 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_116;
// synthesis translate_on
always @(*) begin
litedramcore_cmd_valid <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_111 = dummy_s;
+ dummy_d_116 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_112;
+reg dummy_d_117;
// synthesis translate_on
always @(*) begin
litedramcore_zqcs_executer_start <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_112 = dummy_s;
+ dummy_d_117 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_113;
+reg dummy_d_118;
// synthesis translate_on
always @(*) begin
litedramcore_cmd_last <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_113 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_114;
-// synthesis translate_on
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-// synthesis translate_off
- dummy_d_114 = dummy_s;
+ dummy_d_118 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
// synthesis translate_off
-reg dummy_d_115;
+reg dummy_d_119;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_115 = dummy_s;
+ dummy_d_119 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
// synthesis translate_off
-reg dummy_d_116;
+reg dummy_d_120;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_116 = dummy_s;
+ dummy_d_120 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_117;
+reg dummy_d_121;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_117 = dummy_s;
+ dummy_d_121 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_118;
+reg dummy_d_122;
// synthesis translate_on
always @(*) begin
bankmachine0_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_118 = dummy_s;
+ dummy_d_122 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_119;
+reg dummy_d_123;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine0_row_open <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_119 = dummy_s;
+ dummy_d_123 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_120;
+reg dummy_d_124;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine0_row_close <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_120 = dummy_s;
+ dummy_d_124 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_121;
+reg dummy_d_125;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_121 = dummy_s;
+ dummy_d_125 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_122;
+reg dummy_d_126;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_122 = dummy_s;
+ dummy_d_126 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_123;
+reg dummy_d_127;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_123 = dummy_s;
+ dummy_d_127 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_128;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_124 = dummy_s;
+ dummy_d_128 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_129;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_125 = dummy_s;
+ dummy_d_129 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_130;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_126 = dummy_s;
+ dummy_d_130 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_127;
+reg dummy_d_131;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
case (bankmachine0_state)
1'd1: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_127 = dummy_s;
+ dummy_d_131 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_128;
+reg dummy_d_132;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
end
end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
endcase
// synthesis translate_off
- dummy_d_128 = dummy_s;
+ dummy_d_132 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_129;
+reg dummy_d_133;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_129 = dummy_s;
+ dummy_d_133 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_130;
+reg dummy_d_134;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
case (bankmachine0_state)
1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_130 = dummy_s;
+ dummy_d_134 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_131;
+reg dummy_d_135;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
case (bankmachine0_state)
1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine0_row_opened) begin
if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_131 = dummy_s;
+ dummy_d_135 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
// synthesis translate_off
-reg dummy_d_132;
+reg dummy_d_136;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_132 = dummy_s;
+ dummy_d_136 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
// synthesis translate_off
-reg dummy_d_133;
+reg dummy_d_137;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_133 = dummy_s;
+ dummy_d_137 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_134;
+reg dummy_d_138;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_134 = dummy_s;
+ dummy_d_138 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_139;
// synthesis translate_on
always @(*) begin
bankmachine1_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_135 = dummy_s;
+ dummy_d_139 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_136;
+reg dummy_d_140;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine1_row_open <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_136 = dummy_s;
+ dummy_d_140 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_137;
+reg dummy_d_141;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine1_row_close <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_137 = dummy_s;
+ dummy_d_141 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_138;
+reg dummy_d_142;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_138 = dummy_s;
+ dummy_d_142 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_139;
+reg dummy_d_143;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_139 = dummy_s;
+ dummy_d_143 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_140;
+reg dummy_d_144;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
case (bankmachine1_state)
1'd1: begin
if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_140 = dummy_s;
+ dummy_d_144 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_145;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_141 = dummy_s;
+ dummy_d_145 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_146;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_142 = dummy_s;
+ dummy_d_146 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_147;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_143 = dummy_s;
+ dummy_d_147 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_148;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
case (bankmachine1_state)
1'd1: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_144 = dummy_s;
+ dummy_d_148 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_145;
+reg dummy_d_149;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_145 = dummy_s;
+ dummy_d_149 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_150;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_146 = dummy_s;
+ dummy_d_150 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_151;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
case (bankmachine1_state)
1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_147 = dummy_s;
+ dummy_d_151 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_152;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
case (bankmachine1_state)
1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine1_row_opened) begin
if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_148 = dummy_s;
+ dummy_d_152 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
// synthesis translate_off
-reg dummy_d_149;
+reg dummy_d_153;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_149 = dummy_s;
+ dummy_d_153 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
// synthesis translate_off
-reg dummy_d_150;
+reg dummy_d_154;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_150 = dummy_s;
+ dummy_d_154 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_151;
+reg dummy_d_155;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_151 = dummy_s;
+ dummy_d_155 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_152;
+reg dummy_d_156;
// synthesis translate_on
always @(*) begin
bankmachine2_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_152 = dummy_s;
+ dummy_d_156 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_153;
+reg dummy_d_157;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine2_row_open <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_153 = dummy_s;
+ dummy_d_157 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_154;
+reg dummy_d_158;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine2_row_close <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_154 = dummy_s;
+ dummy_d_158 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_155;
+reg dummy_d_159;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_155 = dummy_s;
+ dummy_d_159 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_156;
+reg dummy_d_160;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_156 = dummy_s;
+ dummy_d_160 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_157;
+reg dummy_d_161;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
case (bankmachine2_state)
1'd1: begin
if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_157 = dummy_s;
+ dummy_d_161 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_158;
+reg dummy_d_162;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_158 = dummy_s;
+ dummy_d_162 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_159;
+reg dummy_d_163;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_159 = dummy_s;
+ dummy_d_163 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_160;
+reg dummy_d_164;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_160 = dummy_s;
+ dummy_d_164 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_161;
+reg dummy_d_165;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
case (bankmachine2_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_161 = dummy_s;
+ dummy_d_165 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_162;
+reg dummy_d_166;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_162 = dummy_s;
+ dummy_d_166 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_163;
+reg dummy_d_167;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_163 = dummy_s;
+ dummy_d_167 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_164;
+reg dummy_d_168;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
case (bankmachine2_state)
1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_164 = dummy_s;
+ dummy_d_168 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_165;
+reg dummy_d_169;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
case (bankmachine2_state)
1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine2_row_opened) begin
if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_165 = dummy_s;
+ dummy_d_169 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
// synthesis translate_off
-reg dummy_d_166;
+reg dummy_d_170;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_166 = dummy_s;
+ dummy_d_170 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
// synthesis translate_off
-reg dummy_d_167;
+reg dummy_d_171;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_167 = dummy_s;
+ dummy_d_171 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_168;
+reg dummy_d_172;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_168 = dummy_s;
+ dummy_d_172 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_169;
+reg dummy_d_173;
// synthesis translate_on
always @(*) begin
bankmachine3_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_169 = dummy_s;
+ dummy_d_173 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_170;
+reg dummy_d_174;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine3_row_open <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_170 = dummy_s;
+ dummy_d_174 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_171;
+reg dummy_d_175;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine3_row_close <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_171 = dummy_s;
+ dummy_d_175 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_172;
+reg dummy_d_176;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_172 = dummy_s;
+ dummy_d_176 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_173;
+reg dummy_d_177;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_173 = dummy_s;
+ dummy_d_177 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_174;
+reg dummy_d_178;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_174 = dummy_s;
+ dummy_d_178 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_179;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_175 = dummy_s;
+ dummy_d_179 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_180;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_176 = dummy_s;
+ dummy_d_180 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_181;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_177 = dummy_s;
+ dummy_d_181 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_182;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
case (bankmachine3_state)
1'd1: begin
end
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_178 = dummy_s;
+ dummy_d_182 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_183;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_179 = dummy_s;
+ dummy_d_183 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_184;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_180 = dummy_s;
+ dummy_d_184 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_185;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
case (bankmachine3_state)
1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_181 = dummy_s;
+ dummy_d_185 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_186;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
case (bankmachine3_state)
1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine3_row_opened) begin
if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_182 = dummy_s;
+ dummy_d_186 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
// synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_187;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_183 = dummy_s;
+ dummy_d_187 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
// synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_188;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_184 = dummy_s;
+ dummy_d_188 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_189;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_185 = dummy_s;
+ dummy_d_189 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_190;
// synthesis translate_on
always @(*) begin
bankmachine4_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_186 = dummy_s;
+ dummy_d_190 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_187;
+reg dummy_d_191;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine4_row_open <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_187 = dummy_s;
+ dummy_d_191 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_188;
+reg dummy_d_192;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine4_row_close <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_188 = dummy_s;
+ dummy_d_192 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_189;
+reg dummy_d_193;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_189 = dummy_s;
+ dummy_d_193 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_190;
+reg dummy_d_194;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_190 = dummy_s;
+ dummy_d_194 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_191;
+reg dummy_d_195;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_191 = dummy_s;
+ dummy_d_195 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_192;
+reg dummy_d_196;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_192 = dummy_s;
+ dummy_d_196 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_193;
+reg dummy_d_197;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_193 = dummy_s;
+ dummy_d_197 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_194;
+reg dummy_d_198;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_194 = dummy_s;
+ dummy_d_198 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_195;
+reg dummy_d_199;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
case (bankmachine4_state)
1'd1: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_195 = dummy_s;
+ dummy_d_199 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_196;
+reg dummy_d_200;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
end
end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
endcase
// synthesis translate_off
- dummy_d_196 = dummy_s;
+ dummy_d_200 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_197;
+reg dummy_d_201;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_197 = dummy_s;
+ dummy_d_201 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_198;
+reg dummy_d_202;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
case (bankmachine4_state)
1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_198 = dummy_s;
+ dummy_d_202 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_199;
+reg dummy_d_203;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
case (bankmachine4_state)
1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine4_row_opened) begin
if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_199 = dummy_s;
+ dummy_d_203 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
// synthesis translate_off
-reg dummy_d_200;
+reg dummy_d_204;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_200 = dummy_s;
+ dummy_d_204 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
// synthesis translate_off
-reg dummy_d_201;
+reg dummy_d_205;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_201 = dummy_s;
+ dummy_d_205 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_202;
+reg dummy_d_206;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_202 = dummy_s;
+ dummy_d_206 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_203;
+reg dummy_d_207;
// synthesis translate_on
always @(*) begin
bankmachine5_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_203 = dummy_s;
+ dummy_d_207 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_204;
+reg dummy_d_208;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine5_row_open <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_204 = dummy_s;
+ dummy_d_208 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_205;
+reg dummy_d_209;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine5_row_close <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_205 = dummy_s;
+ dummy_d_209 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_206;
+reg dummy_d_210;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_206 = dummy_s;
+ dummy_d_210 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_207;
+reg dummy_d_211;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_207 = dummy_s;
+ dummy_d_211 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_208;
+reg dummy_d_212;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
case (bankmachine5_state)
1'd1: begin
if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_208 = dummy_s;
+ dummy_d_212 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_209;
+reg dummy_d_213;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_209 = dummy_s;
+ dummy_d_213 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_210;
+reg dummy_d_214;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_210 = dummy_s;
+ dummy_d_214 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_211;
+reg dummy_d_215;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_211 = dummy_s;
+ dummy_d_215 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_212;
+reg dummy_d_216;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
case (bankmachine5_state)
1'd1: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_212 = dummy_s;
+ dummy_d_216 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_213;
+reg dummy_d_217;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_213 = dummy_s;
+ dummy_d_217 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_218;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_214 = dummy_s;
+ dummy_d_218 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_219;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
case (bankmachine5_state)
1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_215 = dummy_s;
+ dummy_d_219 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_220;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
case (bankmachine5_state)
1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine5_row_opened) begin
if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_216 = dummy_s;
+ dummy_d_220 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
// synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_221;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_217 = dummy_s;
+ dummy_d_221 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
// synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_222;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_218 = dummy_s;
+ dummy_d_222 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_223;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_219 = dummy_s;
+ dummy_d_223 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_220;
+reg dummy_d_224;
// synthesis translate_on
always @(*) begin
bankmachine6_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_220 = dummy_s;
+ dummy_d_224 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_221;
+reg dummy_d_225;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine6_row_open <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_221 = dummy_s;
+ dummy_d_225 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_222;
+reg dummy_d_226;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine6_row_close <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_222 = dummy_s;
+ dummy_d_226 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_223;
+reg dummy_d_227;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_223 = dummy_s;
+ dummy_d_227 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_224;
+reg dummy_d_228;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
end
3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_224 = dummy_s;
+ dummy_d_228 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_225;
+reg dummy_d_229;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
case (bankmachine6_state)
1'd1: begin
if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
end
3'd4: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_225 = dummy_s;
+ dummy_d_229 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_226;
+reg dummy_d_230;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
end
2'd3: begin
if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_226 = dummy_s;
+ dummy_d_230 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_227;
+reg dummy_d_231;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
end
3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_227 = dummy_s;
+ dummy_d_231 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_232;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_228 = dummy_s;
+ dummy_d_232 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_233;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_229 = dummy_s;
+ dummy_d_233 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_234;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_230 = dummy_s;
+ dummy_d_234 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_231;
+reg dummy_d_235;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
case (bankmachine6_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_231 = dummy_s;
+ dummy_d_235 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_232;
+reg dummy_d_236;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
case (bankmachine6_state)
1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_232 = dummy_s;
+ dummy_d_236 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_233;
+reg dummy_d_237;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
case (bankmachine6_state)
1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine6_row_opened) begin
if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_233 = dummy_s;
+ dummy_d_237 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
// synthesis translate_off
-reg dummy_d_234;
+reg dummy_d_238;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
end
// synthesis translate_off
- dummy_d_234 = dummy_s;
+ dummy_d_238 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
// synthesis translate_off
-reg dummy_d_235;
+reg dummy_d_239;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_auto_precharge <= 1'd0;
end
end
// synthesis translate_off
- dummy_d_235 = dummy_s;
+ dummy_d_239 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
// synthesis translate_off
-reg dummy_d_236;
+reg dummy_d_240;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
end
// synthesis translate_off
- dummy_d_236 = dummy_s;
+ dummy_d_240 = dummy_s;
// synthesis translate_on
end
assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
// synthesis translate_off
-reg dummy_d_237;
+reg dummy_d_241;
// synthesis translate_on
always @(*) begin
bankmachine7_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_237 = dummy_s;
+ dummy_d_241 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_238;
+reg dummy_d_242;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ litedramcore_bankmachine7_row_open <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
end
3'd4: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_238 = dummy_s;
+ dummy_d_242 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_239;
+reg dummy_d_243;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ litedramcore_bankmachine7_row_close <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_239 = dummy_s;
+ dummy_d_243 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_240;
+reg dummy_d_244;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_240 = dummy_s;
+ dummy_d_244 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_241;
+reg dummy_d_245;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
end
end
3'd4: begin
end
endcase
// synthesis translate_off
- dummy_d_241 = dummy_s;
+ dummy_d_245 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_242;
+reg dummy_d_246;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
end
3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_242 = dummy_s;
+ dummy_d_246 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_247;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
end
end
3'd4: begin
4'd8: begin
end
default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
end
endcase
// synthesis translate_off
- dummy_d_243 = dummy_s;
+ dummy_d_247 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_248;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
end
3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_244 = dummy_s;
+ dummy_d_248 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_249;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
2'd3: begin
end
3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
end
3'd5: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_245 = dummy_s;
+ dummy_d_249 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_246;
+reg dummy_d_250;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
case (bankmachine7_state)
1'd1: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_246 = dummy_s;
+ dummy_d_250 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_247;
+reg dummy_d_251;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
end
3'd4: begin
end
4'd8: begin
end
default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
end
endcase
// synthesis translate_off
- dummy_d_247 = dummy_s;
+ dummy_d_251 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_248;
+reg dummy_d_252;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
end
2'd2: begin
end
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
end
end else begin
end
end
endcase
// synthesis translate_off
- dummy_d_248 = dummy_s;
+ dummy_d_252 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_249;
+reg dummy_d_253;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
case (bankmachine7_state)
1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
end
2'd2: begin
end
2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
end
3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
end
3'd5: begin
end
end
endcase
// synthesis translate_off
- dummy_d_249 = dummy_s;
+ dummy_d_253 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_250;
+reg dummy_d_254;
// synthesis translate_on
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
case (bankmachine7_state)
1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
2'd2: begin
end
2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
end
3'd4: begin
end
if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
if (litedramcore_bankmachine7_row_opened) begin
if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
end else begin
end
end else begin
end
endcase
// synthesis translate_off
- dummy_d_250 = dummy_s;
+ dummy_d_254 = dummy_s;
// synthesis translate_on
end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
// synthesis translate_off
-reg dummy_d_251;
+reg dummy_d_255;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_valids <= 8'd0;
litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
// synthesis translate_off
- dummy_d_251 = dummy_s;
+ dummy_d_255 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
// synthesis translate_off
-reg dummy_d_252;
+reg dummy_d_256;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
end
// synthesis translate_off
- dummy_d_252 = dummy_s;
+ dummy_d_256 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_253;
+reg dummy_d_257;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
end
// synthesis translate_off
- dummy_d_253 = dummy_s;
+ dummy_d_257 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_254;
+reg dummy_d_258;
// synthesis translate_on
always @(*) begin
litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
end
// synthesis translate_off
- dummy_d_254 = dummy_s;
+ dummy_d_258 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_255;
+reg dummy_d_259;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine0_cmd_ready <= 1'd0;
litedramcore_bankmachine0_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_255 = dummy_s;
+ dummy_d_259 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_256;
+reg dummy_d_260;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine1_cmd_ready <= 1'd0;
litedramcore_bankmachine1_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_256 = dummy_s;
+ dummy_d_260 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_257;
+reg dummy_d_261;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine2_cmd_ready <= 1'd0;
litedramcore_bankmachine2_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_257 = dummy_s;
+ dummy_d_261 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_258;
+reg dummy_d_262;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine3_cmd_ready <= 1'd0;
litedramcore_bankmachine3_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_258 = dummy_s;
+ dummy_d_262 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_259;
+reg dummy_d_263;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine4_cmd_ready <= 1'd0;
litedramcore_bankmachine4_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_259 = dummy_s;
+ dummy_d_263 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_260;
+reg dummy_d_264;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine5_cmd_ready <= 1'd0;
litedramcore_bankmachine5_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_260 = dummy_s;
+ dummy_d_264 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_261;
+reg dummy_d_265;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine6_cmd_ready <= 1'd0;
litedramcore_bankmachine6_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_261 = dummy_s;
+ dummy_d_265 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_262;
+reg dummy_d_266;
// synthesis translate_on
always @(*) begin
litedramcore_bankmachine7_cmd_ready <= 1'd0;
litedramcore_bankmachine7_cmd_ready <= 1'd1;
end
// synthesis translate_off
- dummy_d_262 = dummy_s;
+ dummy_d_266 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
// synthesis translate_off
-reg dummy_d_263;
+reg dummy_d_267;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_valids <= 8'd0;
litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
// synthesis translate_off
- dummy_d_263 = dummy_s;
+ dummy_d_267 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
// synthesis translate_off
-reg dummy_d_264;
+reg dummy_d_268;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_cas <= 1'd0;
litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
end
// synthesis translate_off
- dummy_d_264 = dummy_s;
+ dummy_d_268 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_265;
+reg dummy_d_269;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_ras <= 1'd0;
litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
end
// synthesis translate_off
- dummy_d_265 = dummy_s;
+ dummy_d_269 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_266;
+reg dummy_d_270;
// synthesis translate_on
always @(*) begin
litedramcore_choose_req_cmd_payload_we <= 1'd0;
litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
end
// synthesis translate_off
- dummy_d_266 = dummy_s;
+ dummy_d_270 = dummy_s;
// synthesis translate_on
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
// synthesis translate_off
-reg dummy_d_267;
+reg dummy_d_271;
// synthesis translate_on
always @(*) begin
multiplexer_next_state <= 4'd0;
end
endcase
// synthesis translate_off
- dummy_d_267 = dummy_s;
+ dummy_d_271 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_268;
+reg dummy_d_272;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
+ litedramcore_choose_req_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel2 <= 1'd1;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel2 <= 2'd2;
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
end
endcase
// synthesis translate_off
- dummy_d_268 = dummy_s;
+ dummy_d_272 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_269;
+reg dummy_d_273;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
+ litedramcore_en1 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
+ litedramcore_en1 <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
end
endcase
// synthesis translate_off
- dummy_d_269 = dummy_s;
+ dummy_d_273 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_270;
+reg dummy_d_274;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
+ litedramcore_steerer_sel0 <= 2'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel3 <= 2'd2;
+ litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel3 <= 1'd0;
+ litedramcore_steerer_sel0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_270 = dummy_s;
+ dummy_d_274 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_271;
+reg dummy_d_275;
// synthesis translate_on
always @(*) begin
- litedramcore_en0 <= 1'd0;
+ litedramcore_steerer_sel1 <= 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_en0 <= 1'd1;
+ litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_271 = dummy_s;
+ dummy_d_275 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_272;
+reg dummy_d_276;
// synthesis translate_on
always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
+ litedramcore_steerer_sel2 <= 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd1;
end
2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
+ litedramcore_steerer_sel2 <= 2'd2;
end
endcase
// synthesis translate_off
- dummy_d_272 = dummy_s;
+ dummy_d_276 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_273;
+reg dummy_d_277;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ litedramcore_choose_cmd_want_activates <= 1'd0;
case (multiplexer_state)
1'd1: begin
if (1'd0) begin
end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
end
end
2'd2: begin
default: begin
if (1'd0) begin
end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
end
end
endcase
// synthesis translate_off
- dummy_d_273 = dummy_s;
+ dummy_d_277 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_274;
+reg dummy_d_278;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
+ litedramcore_steerer_sel3 <= 2'd0;
case (multiplexer_state)
1'd1: begin
+ litedramcore_steerer_sel3 <= 2'd2;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
+ litedramcore_steerer_sel3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_274 = dummy_s;
+ dummy_d_278 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_275;
+reg dummy_d_279;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
+ litedramcore_en0 <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ litedramcore_en0 <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_275 = dummy_s;
+ dummy_d_279 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_276;
+reg dummy_d_280;
// synthesis translate_on
always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
+ litedramcore_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
end
2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
end
endcase
// synthesis translate_off
- dummy_d_276 = dummy_s;
+ dummy_d_280 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_277;
+reg dummy_d_281;
// synthesis translate_on
always @(*) begin
- litedramcore_en1 <= 1'd0;
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_en1 <= 1'd1;
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
2'd2: begin
end
4'd10: begin
end
default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
end
endcase
// synthesis translate_off
- dummy_d_277 = dummy_s;
+ dummy_d_281 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_278;
+reg dummy_d_282;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
+ litedramcore_choose_req_want_reads <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
end
2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
end
2'd3: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel0 <= 1'd0;
+ litedramcore_choose_req_want_reads <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_278 = dummy_s;
+ dummy_d_282 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_279;
+reg dummy_d_283;
// synthesis translate_on
always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
+ litedramcore_choose_req_want_writes <= 1'd0;
case (multiplexer_state)
1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
+ litedramcore_choose_req_want_writes <= 1'd1;
end
2'd2: begin
end
4'd10: begin
end
default: begin
- litedramcore_steerer_sel1 <= 1'd1;
end
endcase
// synthesis translate_off
- dummy_d_279 = dummy_s;
+ dummy_d_283 = dummy_s;
// synthesis translate_on
end
assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign user_port_rdata_valid = new_master_rdata_valid8;
// synthesis translate_off
-reg dummy_d_280;
+reg dummy_d_284;
// synthesis translate_on
always @(*) begin
litedramcore_interface_wdata <= 128'd0;
end
endcase
// synthesis translate_off
- dummy_d_280 = dummy_s;
+ dummy_d_284 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_281;
+reg dummy_d_285;
// synthesis translate_on
always @(*) begin
litedramcore_interface_wdata_we <= 16'd0;
end
endcase
// synthesis translate_off
- dummy_d_281 = dummy_s;
+ dummy_d_285 = dummy_s;
// synthesis translate_on
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign roundrobin5_grant = 1'd0;
assign roundrobin6_grant = 1'd0;
assign roundrobin7_grant = 1'd0;
+assign litedramcore_wishbone_adr = wb_bus_adr;
+assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
+assign wb_bus_dat_r = litedramcore_wishbone_dat_r;
+assign litedramcore_wishbone_sel = wb_bus_sel;
+assign litedramcore_wishbone_cyc = wb_bus_cyc;
+assign litedramcore_wishbone_stb = wb_bus_stb;
+assign wb_bus_ack = litedramcore_wishbone_ack;
+assign litedramcore_wishbone_we = wb_bus_we;
+assign litedramcore_wishbone_cti = wb_bus_cti;
+assign litedramcore_wishbone_bte = wb_bus_bte;
+assign wb_bus_err = litedramcore_wishbone_err;
// synthesis translate_off
-reg dummy_d_282;
+reg dummy_d_286;
// synthesis translate_on
always @(*) begin
csrbank0_sel <= 1'd0;
csrbank0_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_282 = dummy_s;
+ dummy_d_286 = dummy_s;
// synthesis translate_on
end
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_init_error0_w = init_error_storage;
// synthesis translate_off
-reg dummy_d_283;
+reg dummy_d_287;
// synthesis translate_on
always @(*) begin
csrbank1_sel <= 1'd0;
csrbank1_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_283 = dummy_s;
+ dummy_d_287 = dummy_s;
// synthesis translate_on
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
// synthesis translate_off
-reg dummy_d_284;
+reg dummy_d_288;
// synthesis translate_on
always @(*) begin
csrbank2_sel <= 1'd0;
csrbank2_sel <= 1'd0;
end
// synthesis translate_off
- dummy_d_284 = dummy_s;
+ dummy_d_288 = dummy_s;
// synthesis translate_on
end
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[31:0];
assign csrbank2_dfii_pi3_rddata_w = litedramcore_phaseinjector3_status[31:0];
assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata_we;
-assign adr = csr_port_adr;
-assign we = csr_port_we;
-assign dat_w = csr_port_dat_w;
-assign csr_port_dat_r = dat_r;
+assign adr = litedramcore_adr;
+assign we = litedramcore_we;
+assign dat_w = litedramcore_dat_w;
+assign litedramcore_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface2_bank_bus_adr = adr;
assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
// synthesis translate_off
-reg dummy_d_285;
+reg dummy_d_289;
// synthesis translate_on
always @(*) begin
rhs_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_285 = dummy_s;
+ dummy_d_289 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_286;
+reg dummy_d_290;
// synthesis translate_on
always @(*) begin
rhs_array_muxed1 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_286 = dummy_s;
+ dummy_d_290 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_287;
+reg dummy_d_291;
// synthesis translate_on
always @(*) begin
rhs_array_muxed2 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_287 = dummy_s;
+ dummy_d_291 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_288;
+reg dummy_d_292;
// synthesis translate_on
always @(*) begin
rhs_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_288 = dummy_s;
+ dummy_d_292 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_289;
+reg dummy_d_293;
// synthesis translate_on
always @(*) begin
rhs_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_289 = dummy_s;
+ dummy_d_293 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_294;
// synthesis translate_on
always @(*) begin
rhs_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_290 = dummy_s;
+ dummy_d_294 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_295;
// synthesis translate_on
always @(*) begin
t_array_muxed0 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_291 = dummy_s;
+ dummy_d_295 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_296;
// synthesis translate_on
always @(*) begin
t_array_muxed1 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_292 = dummy_s;
+ dummy_d_296 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_297;
// synthesis translate_on
always @(*) begin
t_array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_293 = dummy_s;
+ dummy_d_297 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_298;
// synthesis translate_on
always @(*) begin
rhs_array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_294 = dummy_s;
+ dummy_d_298 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_299;
// synthesis translate_on
always @(*) begin
rhs_array_muxed7 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_295 = dummy_s;
+ dummy_d_299 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_300;
// synthesis translate_on
always @(*) begin
rhs_array_muxed8 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_296 = dummy_s;
+ dummy_d_300 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_301;
// synthesis translate_on
always @(*) begin
rhs_array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_297 = dummy_s;
+ dummy_d_301 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_302;
// synthesis translate_on
always @(*) begin
rhs_array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_298 = dummy_s;
+ dummy_d_302 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_299;
+reg dummy_d_303;
// synthesis translate_on
always @(*) begin
rhs_array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_299 = dummy_s;
+ dummy_d_303 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_300;
+reg dummy_d_304;
// synthesis translate_on
always @(*) begin
t_array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_300 = dummy_s;
+ dummy_d_304 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_301;
+reg dummy_d_305;
// synthesis translate_on
always @(*) begin
t_array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_301 = dummy_s;
+ dummy_d_305 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_302;
+reg dummy_d_306;
// synthesis translate_on
always @(*) begin
t_array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_302 = dummy_s;
+ dummy_d_306 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_303;
+reg dummy_d_307;
// synthesis translate_on
always @(*) begin
rhs_array_muxed12 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_303 = dummy_s;
+ dummy_d_307 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_304;
+reg dummy_d_308;
// synthesis translate_on
always @(*) begin
rhs_array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_304 = dummy_s;
+ dummy_d_308 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_305;
+reg dummy_d_309;
// synthesis translate_on
always @(*) begin
rhs_array_muxed14 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_305 = dummy_s;
+ dummy_d_309 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_306;
+reg dummy_d_310;
// synthesis translate_on
always @(*) begin
rhs_array_muxed15 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_306 = dummy_s;
+ dummy_d_310 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_307;
+reg dummy_d_311;
// synthesis translate_on
always @(*) begin
rhs_array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_307 = dummy_s;
+ dummy_d_311 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_308;
+reg dummy_d_312;
// synthesis translate_on
always @(*) begin
rhs_array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_308 = dummy_s;
+ dummy_d_312 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_309;
+reg dummy_d_313;
// synthesis translate_on
always @(*) begin
rhs_array_muxed18 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_309 = dummy_s;
+ dummy_d_313 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_310;
+reg dummy_d_314;
// synthesis translate_on
always @(*) begin
rhs_array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_310 = dummy_s;
+ dummy_d_314 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_311;
+reg dummy_d_315;
// synthesis translate_on
always @(*) begin
rhs_array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_311 = dummy_s;
+ dummy_d_315 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_312;
+reg dummy_d_316;
// synthesis translate_on
always @(*) begin
rhs_array_muxed21 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_312 = dummy_s;
+ dummy_d_316 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_313;
+reg dummy_d_317;
// synthesis translate_on
always @(*) begin
rhs_array_muxed22 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_313 = dummy_s;
+ dummy_d_317 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_314;
+reg dummy_d_318;
// synthesis translate_on
always @(*) begin
rhs_array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_314 = dummy_s;
+ dummy_d_318 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_315;
+reg dummy_d_319;
// synthesis translate_on
always @(*) begin
rhs_array_muxed24 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_315 = dummy_s;
+ dummy_d_319 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_316;
+reg dummy_d_320;
// synthesis translate_on
always @(*) begin
rhs_array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_316 = dummy_s;
+ dummy_d_320 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_317;
+reg dummy_d_321;
// synthesis translate_on
always @(*) begin
rhs_array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_317 = dummy_s;
+ dummy_d_321 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_318;
+reg dummy_d_322;
// synthesis translate_on
always @(*) begin
rhs_array_muxed27 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_318 = dummy_s;
+ dummy_d_322 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_319;
+reg dummy_d_323;
// synthesis translate_on
always @(*) begin
rhs_array_muxed28 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_319 = dummy_s;
+ dummy_d_323 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_320;
+reg dummy_d_324;
// synthesis translate_on
always @(*) begin
rhs_array_muxed29 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_320 = dummy_s;
+ dummy_d_324 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_321;
+reg dummy_d_325;
// synthesis translate_on
always @(*) begin
rhs_array_muxed30 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_321 = dummy_s;
+ dummy_d_325 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_322;
+reg dummy_d_326;
// synthesis translate_on
always @(*) begin
rhs_array_muxed31 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_322 = dummy_s;
+ dummy_d_326 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_323;
+reg dummy_d_327;
// synthesis translate_on
always @(*) begin
rhs_array_muxed32 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_323 = dummy_s;
+ dummy_d_327 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_324;
+reg dummy_d_328;
// synthesis translate_on
always @(*) begin
rhs_array_muxed33 <= 22'd0;
end
endcase
// synthesis translate_off
- dummy_d_324 = dummy_s;
+ dummy_d_328 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_325;
+reg dummy_d_329;
// synthesis translate_on
always @(*) begin
rhs_array_muxed34 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_325 = dummy_s;
+ dummy_d_329 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_326;
+reg dummy_d_330;
// synthesis translate_on
always @(*) begin
rhs_array_muxed35 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_326 = dummy_s;
+ dummy_d_330 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_327;
+reg dummy_d_331;
// synthesis translate_on
always @(*) begin
array_muxed0 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_327 = dummy_s;
+ dummy_d_331 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_328;
+reg dummy_d_332;
// synthesis translate_on
always @(*) begin
array_muxed1 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_328 = dummy_s;
+ dummy_d_332 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_329;
+reg dummy_d_333;
// synthesis translate_on
always @(*) begin
array_muxed2 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_329 = dummy_s;
+ dummy_d_333 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_330;
+reg dummy_d_334;
// synthesis translate_on
always @(*) begin
array_muxed3 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_330 = dummy_s;
+ dummy_d_334 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_331;
+reg dummy_d_335;
// synthesis translate_on
always @(*) begin
array_muxed4 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_331 = dummy_s;
+ dummy_d_335 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_332;
+reg dummy_d_336;
// synthesis translate_on
always @(*) begin
array_muxed5 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_332 = dummy_s;
+ dummy_d_336 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_333;
+reg dummy_d_337;
// synthesis translate_on
always @(*) begin
array_muxed6 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_333 = dummy_s;
+ dummy_d_337 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_334;
+reg dummy_d_338;
// synthesis translate_on
always @(*) begin
array_muxed7 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_334 = dummy_s;
+ dummy_d_338 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_335;
+reg dummy_d_339;
// synthesis translate_on
always @(*) begin
array_muxed8 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_335 = dummy_s;
+ dummy_d_339 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_336;
+reg dummy_d_340;
// synthesis translate_on
always @(*) begin
array_muxed9 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_336 = dummy_s;
+ dummy_d_340 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_337;
+reg dummy_d_341;
// synthesis translate_on
always @(*) begin
array_muxed10 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_337 = dummy_s;
+ dummy_d_341 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_342;
// synthesis translate_on
always @(*) begin
array_muxed11 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_338 = dummy_s;
+ dummy_d_342 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_343;
// synthesis translate_on
always @(*) begin
array_muxed12 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_339 = dummy_s;
+ dummy_d_343 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_344;
// synthesis translate_on
always @(*) begin
array_muxed13 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_340 = dummy_s;
+ dummy_d_344 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_345;
// synthesis translate_on
always @(*) begin
array_muxed14 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_341 = dummy_s;
+ dummy_d_345 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_346;
// synthesis translate_on
always @(*) begin
array_muxed15 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_342 = dummy_s;
+ dummy_d_346 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_347;
// synthesis translate_on
always @(*) begin
array_muxed16 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_343 = dummy_s;
+ dummy_d_347 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_348;
// synthesis translate_on
always @(*) begin
array_muxed17 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_344 = dummy_s;
+ dummy_d_348 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_349;
// synthesis translate_on
always @(*) begin
array_muxed18 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_345 = dummy_s;
+ dummy_d_349 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_350;
// synthesis translate_on
always @(*) begin
array_muxed19 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_346 = dummy_s;
+ dummy_d_350 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_351;
// synthesis translate_on
always @(*) begin
array_muxed20 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_347 = dummy_s;
+ dummy_d_351 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_352;
// synthesis translate_on
always @(*) begin
array_muxed21 <= 3'd0;
end
endcase
// synthesis translate_off
- dummy_d_348 = dummy_s;
+ dummy_d_352 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_353;
// synthesis translate_on
always @(*) begin
array_muxed22 <= 15'd0;
end
endcase
// synthesis translate_off
- dummy_d_349 = dummy_s;
+ dummy_d_353 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_354;
// synthesis translate_on
always @(*) begin
array_muxed23 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_350 = dummy_s;
+ dummy_d_354 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_355;
// synthesis translate_on
always @(*) begin
array_muxed24 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_351 = dummy_s;
+ dummy_d_355 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_356;
// synthesis translate_on
always @(*) begin
array_muxed25 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_352 = dummy_s;
+ dummy_d_356 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_357;
// synthesis translate_on
always @(*) begin
array_muxed26 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_353 = dummy_s;
+ dummy_d_357 = dummy_s;
// synthesis translate_on
end
// synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_358;
// synthesis translate_on
always @(*) begin
array_muxed27 <= 1'd0;
end
endcase
// synthesis translate_off
- dummy_d_354 = dummy_s;
+ dummy_d_358 = dummy_s;
// synthesis translate_on
end
assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
end
always @(posedge sys_clk) begin
+ state <= next_state;
a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip0_value <= 1'd0;
end
- a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]};
+ a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip1_value <= 1'd0;
end
- a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]};
+ a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip2_value <= 1'd0;
end
- a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]};
+ a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip3_value <= 1'd0;
end
- a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]};
+ a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip4_value <= 1'd0;
end
- a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]};
+ a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip5_value <= 1'd0;
end
- a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]};
+ a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip6_value <= 1'd0;
end
- a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]};
+ a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[23:8]};
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip7_value <= 1'd0;
end
- a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]};
+ a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip8_value <= 1'd0;
end
- a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]};
+ a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip9_value <= 1'd0;
end
- a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]};
+ a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip10_value <= 1'd0;
end
- a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]};
+ a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip11_value <= 1'd0;
end
- a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]};
+ a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip12_value <= 1'd0;
end
- a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]};
+ a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip13_value <= 1'd0;
end
- a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]};
+ a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip14_value <= 1'd0;
end
- a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]};
+ a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[23:8]};
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
end
if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
a7ddrphy_bitslip15_value <= 1'd0;
end
- a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]};
+ a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[23:8]};
if (litedramcore_inti_p0_rddata_valid) begin
litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
end
a7ddrphy_dqs_oe_delayed <= 1'd0;
a7ddrphy_dqspattern_o1 <= 8'd0;
a7ddrphy_dq_oe_delayed <= 1'd0;
- a7ddrphy_bitslip0_value <= 3'd0;
- a7ddrphy_bitslip1_value <= 3'd0;
- a7ddrphy_bitslip2_value <= 3'd0;
- a7ddrphy_bitslip3_value <= 3'd0;
- a7ddrphy_bitslip4_value <= 3'd0;
- a7ddrphy_bitslip5_value <= 3'd0;
- a7ddrphy_bitslip6_value <= 3'd0;
- a7ddrphy_bitslip7_value <= 3'd0;
- a7ddrphy_bitslip8_value <= 3'd0;
- a7ddrphy_bitslip9_value <= 3'd0;
- a7ddrphy_bitslip10_value <= 3'd0;
- a7ddrphy_bitslip11_value <= 3'd0;
- a7ddrphy_bitslip12_value <= 3'd0;
- a7ddrphy_bitslip13_value <= 3'd0;
- a7ddrphy_bitslip14_value <= 3'd0;
- a7ddrphy_bitslip15_value <= 3'd0;
+ a7ddrphy_bitslip0_value <= 4'd0;
+ a7ddrphy_bitslip1_value <= 4'd0;
+ a7ddrphy_bitslip2_value <= 4'd0;
+ a7ddrphy_bitslip3_value <= 4'd0;
+ a7ddrphy_bitslip4_value <= 4'd0;
+ a7ddrphy_bitslip5_value <= 4'd0;
+ a7ddrphy_bitslip6_value <= 4'd0;
+ a7ddrphy_bitslip7_value <= 4'd0;
+ a7ddrphy_bitslip8_value <= 4'd0;
+ a7ddrphy_bitslip9_value <= 4'd0;
+ a7ddrphy_bitslip10_value <= 4'd0;
+ a7ddrphy_bitslip11_value <= 4'd0;
+ a7ddrphy_bitslip12_value <= 4'd0;
+ a7ddrphy_bitslip13_value <= 4'd0;
+ a7ddrphy_bitslip14_value <= 4'd0;
+ a7ddrphy_bitslip15_value <= 4'd0;
a7ddrphy_rddata_en_last <= 8'd0;
a7ddrphy_wrdata_en_last <= 4'd0;
litedramcore_storage <= 4'd0;
init_done_re <= 1'd0;
init_error_storage <= 1'd0;
init_error_re <= 1'd0;
+ state <= 1'd0;
refresher_state <= 2'd0;
bankmachine0_state <= 4'd0;
bankmachine1_state <= 4'd0;
projects / microwatt.git / commitdiff