arch-x86, arch-power: fix calls to bits and insertBits

The bits and insertBits assume the first bit is the larger bit and the last
bit is the smaller bit.  This commit fixes several X86 and Power calls to
these functions that incorrectly assumed that first was the smaller bit.

Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01
Reviewed-on: https://gem5-review.googlesource.com/10241
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 71ef95b06709ede4a1bea907883fac3e10741ba9..6bc19adb9375fac72c1393e1ef3d3d4bcf2a8f08 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -158,8 +158,8 @@ decode OPCODE default Unknown::unknown() {
             508: cmpb({{
                 uint32_t val = 0;
                 for (int n = 0; n < 32; n += 8) {
-                    if(bits(Rs, n, n+7) == bits(Rb, n, n+7)) {
-                        val = insertBits(val, n, n+7, 0xff);
+                    if(bits(Rs, n+7, n) == bits(Rb, n+7, n)) {
+                        val = insertBits(val, n+7, n, 0xff);
                     }
                 }
                 Ra = val;
@@ -580,8 +580,8 @@ decode OPCODE default Unknown::unknown() {
                         for (int i = 0; i < 8; ++i) {
                             if (bits(FLM, i) == 1) {
                                 int k = 4 * (i + (8 * (1 - W_FIELD)));
-                                FPSCR = insertBits(FPSCR, k, k + 3,
-                                                   bits(Fb_uq, k, k + 3));
+                                FPSCR = insertBits(FPSCR, k + 3, k,
+                                                   bits(Fb_uq, k + 3, k));
                             }
                         }
                     }

diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 28c50f358a4d594868aa6a4153679252b9dd1e4c..a866b950f0221bc755d37043703397a98a176dd5 100644 (file)
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -145,7 +145,7 @@ ISA::readMiscReg(int miscReg, ThreadContext * tc)
     if (miscReg == MISCREG_FSW) {
         MiscReg fsw = regVal[MISCREG_FSW];
         MiscReg top = regVal[MISCREG_X87_TOP];
-        return insertBits(fsw, 11, 13, top);
+        return insertBits(fsw, 13, 11, top);
     }
 
     return readMiscRegNoEffect(miscReg);