+2010-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/44615
+ * config/i386/atom.md (atom_sseishft_2): Also check sseishft1.
+
+ * config/i386/i386.md (type): Add sseishft1
+
+ * config/i386/ppro_insn (ppro_insn): Also check sseishft1.
+ (ppro_insn_load): Likewise.
+ (ppro_insn_store): Likewise.
+ (ppro_insn_both): Likewise.
+
+ * config/i386/sse.md (sse2_lshrv1ti3): Add atom_unit.
+ (*vec_extractv2di_1_rex64_avx): Replace sseishft with sseishft1
+ for type.
+ (*vec_extractv2di_1_avx): Likewise.
+ (*vec_extractv2di_1_rex64): Replace sseishft with sseishft1 for
+ type. Remove atom_unit.
+ (*vec_extractv2di_1_sse2): Likewise.
+
2010-06-21 DJ Delorie <dj@redhat.com>
* diagnostic.h (diagnostic_classification_change_t): New.
;; if palignr or psrldq
(define_insn_reservation "atom_sseishft_2" 1
(and (eq_attr "cpu" "atom")
- (and (eq_attr "type" "sseishft")
- (and (eq_attr "atom_unit" "sishuf")
- (match_operand 2 "immediate_operand"))))
+ (ior (eq_attr "type" "sseishft1")
+ (and (eq_attr "type" "sseishft")
+ (and (eq_attr "atom_unit" "sishuf")
+ (match_operand 2 "immediate_operand")))))
"atom-simple-0")
;; if reg/mem op
push,pop,call,callv,leave,
str,bitmanip,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
- sselog,sselog1,sseiadd,sseiadd1,sseishft,sseimul,
+ sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
ssemuladd,sse4arg,lwp,
mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
(define_insn_reservation "ppro_insn" 1
(and (eq_attr "cpu" "pentiumpro")
(and (eq_attr "memory" "none,unknown")
- (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+ (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
"decodern,(p0|p1)")
;; read-modify and register-memory instructions have 2 or three uops,
(define_insn_reservation "ppro_insn_load" 3
(and (eq_attr "cpu" "pentiumpro")
(and (eq_attr "memory" "load")
- (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+ (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
"decoder0,p2+(p0|p1)")
(define_insn_reservation "ppro_insn_store" 1
(and (eq_attr "cpu" "pentiumpro")
(and (eq_attr "memory" "store")
- (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+ (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
"decoder0,(p0|p1),p4+p3")
;; read-modify-store instructions produce 4 uops so they have to be
(define_insn_reservation "ppro_insn_both" 4
(and (eq_attr "cpu" "pentiumpro")
(and (eq_attr "memory" "both")
- (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseimul,mmx,mmxadd,mmxcmp")))
+ (eq_attr "type" "alu,alu1,negnot,incdec,icmp,test,setcc,icmov,push,pop,fxch,sseiadd,sseishft,sseishft1,sseimul,mmx,mmxadd,mmxcmp")))
"decoder0,p2+(p0|p1),p4+p3")
[(set_attr "type" "sseishft")
(set_attr "prefix_data16" "1")
(set_attr "length_immediate" "1")
+ (set_attr "atom_unit" "sishuf")
(set_attr "mode" "TI")])
(define_insn "lshr<mode>3"
vpsrldq\t{$8, %1, %0|%0, %1, 8}
vmovq\t{%H1, %0|%0, %H1}
vmov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+ [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
(set_attr "length_immediate" "*,1,*,*")
(set_attr "memory" "*,none,*,*")
(set_attr "prefix" "vex")
psrldq\t{$8, %0|%0, 8}
movq\t{%H1, %0|%0, %H1}
mov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+ [(set_attr "type" "ssemov,sseishft1,ssemov,imov")
(set_attr "length_immediate" "*,1,*,*")
- (set_attr "atom_unit" "*,sishuf,*,*")
(set_attr "memory" "*,none,*,*")
(set_attr "mode" "V2SF,TI,TI,DI")])
vmovhps\t{%1, %0|%0, %1}
vpsrldq\t{$8, %1, %0|%0, %1, 8}
vmovq\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft,ssemov")
+ [(set_attr "type" "ssemov,sseishft1,ssemov")
(set_attr "length_immediate" "*,1,*")
(set_attr "memory" "*,none,*")
(set_attr "prefix" "vex")
movhps\t{%1, %0|%0, %1}
psrldq\t{$8, %0|%0, 8}
movq\t{%H1, %0|%0, %H1}"
- [(set_attr "type" "ssemov,sseishft,ssemov")
+ [(set_attr "type" "ssemov,sseishft1,ssemov")
(set_attr "length_immediate" "*,1,*")
- (set_attr "atom_unit" "*,sishuf,*")
(set_attr "memory" "*,none,*")
(set_attr "mode" "V2SF,TI,TI")])
+2010-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR target/44615
+ * gcc.target/i386/sse2-vec-2a.c: New.
+
2010-06-21 DJ Delorie <dj@redhat.com>
* gcc.dg/pragma-diag-1.c: New.
--- /dev/null
+/* { dg-do run } */
+/* { dg-options "-O2 -msse2 -mtune=atom" } */
+/* { dg-require-effective-target sse2 } */
+
+#include "sse2-vec-2.c"