Add tests for logger pass

diff --git a/tests/various/logger_error.ys b/tests/various/logger_error.ys
new file mode 100644 (file)
index 0000000..46fe7f5
--- /dev/null
+++ b/tests/various/logger_error.ys
@@ -0,0 +1,6 @@
+logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
+read_verilog << EOF
+module top(...);
+       assign b = w;
+endmodule
+EOF

diff --git a/tests/various/logger_nowarning.ys b/tests/various/logger_nowarning.ys
new file mode 100644 (file)
index 0000000..87cbbc6
--- /dev/null
+++ b/tests/various/logger_nowarning.ys
@@ -0,0 +1,6 @@
+logger -expect-no-warnings -nowarn "is implicitly declared."
+read_verilog << EOF
+module top(...);
+       assign b = w;
+endmodule
+EOF

diff --git a/tests/various/logger_warn.ys b/tests/various/logger_warn.ys
new file mode 100644 (file)
index 0000000..2316ae4
--- /dev/null
+++ b/tests/various/logger_warn.ys
@@ -0,0 +1,6 @@
+logger -warn "Successfully finished Verilog frontend." -expect warning "Successfully finished Verilog frontend." 1
+read_verilog << EOF
+module top(...);
+       assign b = w;
+endmodule
+EOF

diff --git a/tests/various/logger_warning.ys b/tests/various/logger_warning.ys
new file mode 100644 (file)
index 0000000..642b1b9
--- /dev/null
+++ b/tests/various/logger_warning.ys
@@ -0,0 +1,6 @@
+logger -expect warning "is implicitly declared." 2
+read_verilog << EOF
+module top(...);
+       assign b = w;
+endmodule
+EOF