arch-arm: implement VMINNM scalar thumb

VMINNM was implemented at Iabbbca2932557cf6c98ce36690c385c3ddf39ed8 but
the thumb scalar encoding was missing. This patch implements it.

Change-Id: Ia29ec77dbd82f6be6b3d040a0e737794f52c33bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19108
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index da439acb8051f6ea7b2fc264a73cdbbb75b01766..434a69c3295d298158e4906574ffb44ae6003a56 100644 (file)
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2539,6 +2539,23 @@ let {{
                 }
             }
           case 0x8:
+            if (machInst.condCode == 0xF) {
+                const bool op = bits(machInst, 6);
+                const uint32_t size = bits(machInst, 9, 8);
+                if (op) {
+                    if (size == 1) {
+                        return new FailUnimplemented("vminnm.f16", machInst);
+                    }
+                    return decodeNeonSizeSingleDouble<VminnmS, VminnmD>(
+                        size, machInst, vd, vn, vm);
+                } else {
+                    if (size == 1) {
+                        return new FailUnimplemented("vmaxnm.f16", machInst);
+                    }
+                    return decodeNeonSizeSingleDouble<VmaxnmS, VmaxnmD>(
+                        size, machInst, vd, vn, vm);
+                }
+            }
             if ((opc3 & 0x1) == 0) {
                 if (single) {
                     return decodeVfpRegRegRegOp<VdivS>(