Fix SYNTHESIS always being defined in Verilog frontend

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index ea23139e23ab7e5835a8feaf0e706bbce3ab7a82..752f7a7a8c0cbf373c415102e3e3d36f931b9e56 100644 (file)
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -321,7 +321,6 @@ struct define_body_t
 define_map_t::define_map_t()
 {
        add("YOSYS", "1");
-       add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
 }
 
 // We must define this destructor here (rather than relying on the default), because we need to

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 2e9c9b2e2e9e95b856dfca627c150968a1bdabc4..5319a45ad16ac1605e71116d3c803a967fde01ce 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -446,6 +446,9 @@ struct VerilogFrontend : public Frontend {
                        }
                        break;
                }
+
+               defines_map.add(formal_mode ? "FORMAL" : "SYNTHESIS", "1");
+
                extra_args(f, filename, args, argidx);
 
                log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());