liteXXX cores: remove Identifier duplication

diff --git a/misoclib/com/liteeth/example_designs/targets/__init__.py b/misoclib/com/liteeth/example_designs/targets/__init__.py
index 75aca8636d656fd491ba506709c5097c43140b1a..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/misoclib/com/liteeth/example_designs/targets/__init__.py
+++ b/misoclib/com/liteeth/example_designs/targets/__init__.py
@@ -1,26 +0,0 @@
-import subprocess
-
-from migen.fhdl.std import *
-from migen.bank.description import *
-
-def get_id():
-       output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
-       return int(output[:8], 16)
-
-class Identifier(Module, AutoCSR):
-       def __init__(self, sysid, frequency, revision=None):
-               self._sysid = CSRStatus(16)
-               self._revision = CSRStatus(32)
-               self._frequency = CSRStatus(32)
-
-               ###
-
-               if revision is None:
-                       revision = get_id()
-
-               self.comb += [
-                       self._sysid.status.eq(sysid),
-                       self._revision.status.eq(revision),
-                       self._frequency.status.eq(frequency),
-               ]
-

diff --git a/misoclib/mem/litesata/example_designs/targets/__init__.py b/misoclib/mem/litesata/example_designs/targets/__init__.py
index 85efe5d95f5b4b86fef0ca348005cd7a2a2f6c27..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/__init__.py
+++ b/misoclib/mem/litesata/example_designs/targets/__init__.py
@@ -1,26 +0,0 @@
-import subprocess
-
-from migen.fhdl.std import *
-from migen.bank.description import *
-
-def get_id():
-       output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
-       return int(output[:8], 16)
-
-class Identifier(Module, AutoCSR):
-       def __init__(self, sysid, frequency, revision=None):
-               self._r_sysid = CSRStatus(16)
-               self._r_revision = CSRStatus(32)
-               self._r_frequency = CSRStatus(32)
-
-               ###
-
-               if revision is None:
-                       revision = get_id()
-
-               self.comb += [
-                       self._r_sysid.status.eq(sysid),
-                       self._r_revision.status.eq(revision),
-                       self._r_frequency.status.eq(frequency),
-               ]
-

diff --git a/misoclib/tools/litescope/example_designs/targets/__init__.py b/misoclib/tools/litescope/example_designs/targets/__init__.py
index 85efe5d95f5b4b86fef0ca348005cd7a2a2f6c27..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
--- a/misoclib/tools/litescope/example_designs/targets/__init__.py
+++ b/misoclib/tools/litescope/example_designs/targets/__init__.py
@@ -1,26 +0,0 @@
-import subprocess
-
-from migen.fhdl.std import *
-from migen.bank.description import *
-
-def get_id():
-       output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
-       return int(output[:8], 16)
-
-class Identifier(Module, AutoCSR):
-       def __init__(self, sysid, frequency, revision=None):
-               self._r_sysid = CSRStatus(16)
-               self._r_revision = CSRStatus(32)
-               self._r_frequency = CSRStatus(32)
-
-               ###
-
-               if revision is None:
-                       revision = get_id()
-
-               self.comb += [
-                       self._r_sysid.status.eq(sysid),
-                       self._r_revision.status.eq(revision),
-                       self._r_frequency.status.eq(frequency),
-               ]
-