(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 08f6743f95eaaf8f3c8d929a01ffd1053559356a..20443bfd7221b9290c429971f8d008e953b70052 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -160,7 +160,10 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 # Simple-V Architectural Resources
 
 * No new Interrupt types are required.
-  (**No modifications to existing Power ISA opcodes are required either**).
+* No modifications to existing Power ISA opcodes are required either.
+* No new Register Files are required (because Simple-V is a category of
+  Zero-Overhead Looping on top of existing instructions and
+  existing registers, not an actual Vector ISA)
 * GPR FPR and CR Field Register extend to 128.  A future
   version may extend to 256 or beyond[^extend] or also extend VSX[^futurevsx]
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)