vendor.lattice_ecp5: Add support for io with xdr=7

This adds support for IOs with xdr=7 using the
IODDR71B and ODDR71B primitives.

diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py
index 0abeba95dc1b830efa1c7835be581908438d81d9..22526d33592ac84f2a3232da0a80104ed0eebc23 100644 (file)
--- a/nmigen/vendor/lattice_ecp5.py
+++ b/nmigen/vendor/lattice_ecp5.py
@@ -399,6 +399,17 @@ class LatticeECP5Platform(TemplatedPlatform):
                     o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit]
                 )
 
+        def get_iddr71b(sclk, eclk, d, q0, q1, q2, q3, q4, q5, q6):
+            for bit in range(len(d)):
+                m.submodules += Instance("IDDR71B",
+                    i_SCLK=sclk,
+                    i_ECLK=eclk,
+                    i_RST=Const(0),
+                    i_D=d[bit],
+                    o_Q0=q0[bit], o_Q1=q1[bit], o_Q2=q2[bit], o_Q3=q3[bit],
+                    o_Q4=q4[bit], o_Q5=q5[bit], o_Q6=q6[bit],
+                )
+
         def get_oddr(sclk, d0, d1, q):
             for bit in range(len(q)):
                 m.submodules += Instance("ODDRX1F",
@@ -418,6 +429,17 @@ class LatticeECP5Platform(TemplatedPlatform):
                     o_Q=q[bit]
                 )
 
+        def get_oddr71b(sclk, eclk, d0, d1, d2, d3, d4, d5, d6, q):
+            for bit in range(len(q)):
+                m.submodules += Instance("ODDR71B",
+                    i_SCLK=sclk,
+                    i_ECLK=eclk,
+                    i_RST=Const(0),
+                    i_D0=d0[bit], i_D1=d1[bit], i_D2=d2[bit], i_D3=d3[bit],
+                    i_D4=d4[bit], i_D5=d5[bit], i_D6=d6[bit],
+                    o_Q=q[bit]
+                )
+
         def get_ineg(z, invert):
             if invert:
                 a = Signal.like(z, name_suffix="_n")
@@ -445,6 +467,14 @@ class LatticeECP5Platform(TemplatedPlatform):
                 pin_i1 = get_ineg(pin.i1, i_invert)
                 pin_i2 = get_ineg(pin.i2, i_invert)
                 pin_i3 = get_ineg(pin.i3, i_invert)
+            elif pin.xdr == 7:
+                pin_i0 = get_ineg(pin.i0, i_invert)
+                pin_i1 = get_ineg(pin.i1, i_invert)
+                pin_i2 = get_ineg(pin.i2, i_invert)
+                pin_i3 = get_ineg(pin.i3, i_invert)
+                pin_i4 = get_ineg(pin.i4, i_invert)
+                pin_i5 = get_ineg(pin.i5, i_invert)
+                pin_i6 = get_ineg(pin.i6, i_invert)
         if "o" in pin.dir:
             if pin.xdr < 2:
                 pin_o  = get_oneg(pin.o,  o_invert)
@@ -456,6 +486,14 @@ class LatticeECP5Platform(TemplatedPlatform):
                 pin_o1 = get_oneg(pin.o1, o_invert)
                 pin_o2 = get_oneg(pin.o2, o_invert)
                 pin_o3 = get_oneg(pin.o3, o_invert)
+            elif pin.xdr == 7:
+                pin_o0 = get_oneg(pin.o0, o_invert)
+                pin_o1 = get_oneg(pin.o1, o_invert)
+                pin_o2 = get_oneg(pin.o2, o_invert)
+                pin_o3 = get_oneg(pin.o3, o_invert)
+                pin_o4 = get_oneg(pin.o4, o_invert)
+                pin_o5 = get_oneg(pin.o5, o_invert)
+                pin_o6 = get_oneg(pin.o6, o_invert)
 
         i = o = t = None
         if "i" in pin.dir:
@@ -497,6 +535,13 @@ class LatticeECP5Platform(TemplatedPlatform):
                 get_oddrx2(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, o)
             if pin.dir in ("oe", "io"):
                 get_oreg(pin.o_clk, ~pin.oe, t)
+        elif pin.xdr == 7:
+            if "i" in pin.dir:
+                get_iddr71b(pin.i_clk, pin.i_fclk, i, pin_i0, pin_i1, pin_i2, pin_i3, pin_i4, pin_i5, pin_i6)
+            if "o" in pin.dir:
+                get_oddr71b(pin.o_clk, pin.o_fclk, pin_o0, pin_o1, pin_o2, pin_o3, pin_o4, pin_o5, pin_o6, o)
+            if pin.dir in ("oe", "io"):
+                get_oreg(pin.o_clk, ~pin.oe, t)
         else:
             assert False
 
@@ -504,7 +549,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_input(self, pin, port, attrs, invert):
         self._check_feature("single-ended input", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
         for bit in range(len(port)):
@@ -516,7 +561,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_output(self, pin, port, attrs, invert):
         self._check_feature("single-ended output", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
         for bit in range(len(port)):
@@ -528,7 +573,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_tristate(self, pin, port, attrs, invert):
         self._check_feature("single-ended tristate", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
         for bit in range(len(port)):
@@ -541,7 +586,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_input_output(self, pin, port, attrs, invert):
         self._check_feature("single-ended input/output", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
         for bit in range(len(port)):
@@ -555,7 +600,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_diff_input(self, pin, p_port, n_port, attrs, invert):
         self._check_feature("differential input", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert)
         for bit in range(len(p_port)):
@@ -567,7 +612,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_diff_output(self, pin, p_port, n_port, attrs, invert):
         self._check_feature("differential output", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
         for bit in range(len(p_port)):
@@ -579,7 +624,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_diff_tristate(self, pin, p_port, n_port, attrs, invert):
         self._check_feature("differential tristate", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, o_invert=invert)
         for bit in range(len(p_port)):
@@ -592,7 +637,7 @@ class LatticeECP5Platform(TemplatedPlatform):
 
     def get_diff_input_output(self, pin, p_port, n_port, attrs, invert):
         self._check_feature("differential input/output", pin, attrs,
-                            valid_xdrs=(0, 1, 2, 4), valid_attrs=True)
+                            valid_xdrs=(0, 1, 2, 4, 7), valid_attrs=True)
         m = Module()
         i, o, t = self._get_xdr_buffer(m, pin, i_invert=invert, o_invert=invert)
         for bit in range(len(p_port)):