add example code

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index e3a951273cba93ff6f5eba60dc740af2e706c226..eafc4267bd276aaedb9ab6d1951732ddc0faa1b6 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -47,7 +47,7 @@
   Where SIMD Goes Wrong:\vspace{10pt}
    \begin{itemize}
    \item See "SIMD instructions considered harmful"
-   https://www.sigarch.org/simd-instructions-considered-harmful
+   https://sigarch.org/simd-instructions-considered-harmful
    \item Corner-cases alone are extremely complex.\\
             Hardware is easy, but software is hell.
    \item O($N^{6}$) ISA opcode proliferation!\\
@@ -569,7 +569,7 @@ function op\_mv(rd, rs) # MV not VMV!
 
   \begin{itemize}
    \item See "SIMD Considered Harmful" for SIMD/RVV analysis\\
-          https://www.sigarch.org/simd-instructions-considered-harmful/
+          https://sigarch.org/simd-instructions-considered-harmful/
   \end{itemize}