add SWAR acronym

diff --git a/svp64-primer/acronyms.tex b/svp64-primer/acronyms.tex
index 66b8ba49476bd226908a92bbb571cffcbc7774a7..99d84855479f2d3482636c6c4daad673268c5645 100644 (file)
--- a/svp64-primer/acronyms.tex
+++ b/svp64-primer/acronyms.tex
@@ -12,6 +12,7 @@
        \acro{MMX}{Intel's first SIMD implementation}
        \acro{RVV}{RISC-V Vector extension}
        \acro{SIMD}{Single Instruction Multiple Data}
+       \acro{SWAR}{SIMD Within A Register (see Flynn's Taxonomy)}
        \acro{SV}{(Scalable) Simple Vectorisation or Simple-V}
        \acro{SVE2}{ARM Scalable Vector Extension version two}
        \acro{SVP64}{Simple-V with Prefixing of Power ISA, 64-bits in length}

diff --git a/svp64-primer/summary.tex b/svp64-primer/summary.tex
index d71686a80fa4a90ebb853b20d7a674d29ad0e07f..2dd482882355345626b350ff9c97977d33fcfea1 100644 (file)
--- a/svp64-primer/summary.tex
+++ b/svp64-primer/summary.tex
@@ -53,8 +53,9 @@ the Power ISA's Supercomputing pedigree.
 registers of 64-bit length into smaller 8-, 16-, 32-bit pieces.
 \cite{SIMD_HARM}\cite{SIMD_HPC}
 These partitions can then be operated on simultaneously, and the initial values 
-and results being stored as entire 64-bit registers. The SIMD instruction opcode
- includes the data width and the operation to perform.
+and results being stored as entire 64-bit registers (\acs{SWAR}).
+The SIMD instruction opcode
+includes the data width and the operation to perform.
 \par
 
 \begin{figure}[hb]