fhdl: support expressions in instance ports

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 27d7bdcb989d9300a5cf43c4295a0b0dab9c9e7c..d6eb990a5e0b9e87f2055a24e1408e44fb59c67d 100644 (file)
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -253,14 +253,14 @@ class Instance:
                self.items = items
        
        class _IO:
-               def __init__(self, name, signal_or_bv):
+               def __init__(self, name, expr=BV(1)):
                        self.name = name
-                       if isinstance(signal_or_bv, Signal):
-                               self.signal = signal_or_bv
-                       elif isinstance(signal_or_bv, BV):
-                               self.signal = Signal(signal_or_bv, name)
+                       if isinstance(expr, BV):
+                               self.expr = Signal(expr, name)
+                       elif isinstance(expr, int):
+                               self.expr = Constant(expr)
                        else:
-                               raise TypeError
+                               self.expr = expr
        class Input(_IO):
                pass    
        class Output(_IO):

diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index ebecf2bbf5ddc3c6b2fdb7daa28ddb1eaa061d8b..0b12692138e2f58028c0a071d3b1ec4a43254bf6 100644 (file)
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -90,11 +90,15 @@ def list_inst_ios(i, ins, outs, inouts):
                else:
                        return set()
        else:
-               return set(item.signal for item in filter(lambda x:
+               subsets = [list_signals(item.expr) for item in filter(lambda x:
                        (ins and isinstance(x, Instance.Input))
                        or (outs and isinstance(x, Instance.Output))
                        or (inouts and isinstance(x, Instance.InOut)),
-                       i.items))
+                       i.items)]
+               if subsets:
+                       return set.union(*subsets)
+               else:
+                       return set()
 
 def list_mem_ios(m, ins, outs):
        if isinstance(m, Fragment):

diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
index e48875f78180f36a444c221bd031692996e79e61..8373e0122b7e559a4a0600df649f033948a7f629 100644 (file)
--- a/migen/fhdl/verilog.py
+++ b/migen/fhdl/verilog.py
@@ -206,7 +206,7 @@ def _printinstances(f, ns, clock_domains):
                for p in x.items:
                        if isinstance(p, Instance._IO):
                                name_inst = p.name
-                               name_design = ns.get_name(p.signal)
+                               name_design = _printexpr(ns, p.expr)
                        elif isinstance(p, Instance.ClockPort):
                                name_inst = p.name_inst
                                name_design = ns.get_name(clock_domains[p.domain].clk)