Make genvar a signed type

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 4895d03020e2a0be281ff6a0b77875ab9fe7172c..d89b2dc88e74575e0fc29aef42442f60371fbab1 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -517,6 +517,7 @@ wire_type_token:
        TOK_GENVAR {
                astbuf3->type = AST_GENVAR;
                astbuf3->is_reg = true;
+               astbuf3->is_signed = true;
                astbuf3->range_left = 31;
                astbuf3->range_right = 0;
        } |