[sim] fixed bug in which shift operands were reversed

diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h
index 59da49de6f92a6abcb1e03f76088fd6351f7207b..8b6bc700f0bbbcfd76a6b58607d7ba799c4c6889 100644 (file)
--- a/riscv/insns/sll.h
+++ b/riscv/insns/sll.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS2 << (RS1 & 0x3F);
+RDR = RS1 << (RS2 & 0x3F);

diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h
index 3d96b0fb21ce02a7dead68d78707527b8222cc4c..521c0f7e5eb8b8f3f03adabd23fa2fce4fbff19d 100644 (file)
--- a/riscv/insns/sllw.h
+++ b/riscv/insns/sllw.h
@@ -1 +1 @@
-RDR = sext32(RS2 << (RS1 & 0x1F));
+RDR = sext32(RS1 << (RS2 & 0x1F));

diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h
index 6dfde0f49decdea983043473f1a1a4a4044c16e2..f0919badbc7f5c045fa124f08dca96ab05e26016 100644 (file)
--- a/riscv/insns/sra.h
+++ b/riscv/insns/sra.h
@@ -1,2 +1,2 @@
 require64;
-RDR = sreg_t(RS2) >> (RS1 & 0x3F);
+RDR = sreg_t(RS1) >> (RS2 & 0x3F);

diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h
index 111f6328aeff8b4d4911796246ec7278bc69f9bb..a49ead6ff1ae3d67af28a45ce921d4b7de7091ad 100644 (file)
--- a/riscv/insns/sraw.h
+++ b/riscv/insns/sraw.h
@@ -1 +1 @@
-RDR = sext32(sreg_t(RS2) >> (RS1 & 0x1F));
+RDR = sext32(sreg_t(RS1) >> (RS2 & 0x1F));

diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h
index 1512be95135b2872266343ed9a5a78c571fd2475..fa17eb71eccae0159712beb743a81689eb2ff77d 100644 (file)
--- a/riscv/insns/srl.h
+++ b/riscv/insns/srl.h
@@ -1,2 +1,2 @@
 require64;
-RDR = RS2 >> (RS1 & 0x3F);
+RDR = RS1 >> (RS2 & 0x3F);

diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 2d9de89f968653864bd94cb8551e526a6dc1f958..7aa4bc6ea5c9ccf99466decca6f3274a0f9739dc 100644 (file)
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RDR = sext32((uint32_t)RS2 >> (RS1 & 0x1F));
+RDR = sext32((uint32_t)RS1 >> (RS2 & 0x1F));