2017-02-18 Jakub Jelinek <jakub@redhat.com>
+ PR target/79569
+ * config/i386/i386.opt (m3dnowa): Replace Undocumented with Report.
+ * common/config/i386/i386-common.c (OPTION_MASK_ISA_3DNOW_A_SET): Define.
+ (ix86_handle_option): Handle OPT_m3dnowa.
+ * doc/invoke.texi (-m3dnowa): Document.
+ * doc/extend.texi (__builtin_ia32_pmulhuw, __builtin_ia32_pf2iw): Use
+ -m3dnowa instead of -m3dnow -march=athlon.
+
PR target/79559
* config/i386/i386.c (ix86_print_operand): Use output_operand_lossage
instead of gcc_assert for K, r and R code checks. Formatting fixes.
#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
#define OPTION_MASK_ISA_3DNOW_SET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
+#define OPTION_MASK_ISA_3DNOW_A_SET \
+ (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
#define OPTION_MASK_ISA_SSE2_SET \
return true;
case OPT_m3dnowa:
- return false;
+ if (value)
+ {
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
+ }
+ else
+ {
+ opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
+ opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
+ }
+ return true;
case OPT_msse:
if (value)
Support 3DNow! built-in functions.
m3dnowa
-Target Undocumented Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
+Target Report Mask(ISA_3DNOW_A) Var(ix86_isa_flags) Save
Support Athlon 3Dnow! built-in functions.
msse
@end smallexample
The following built-in functions are made available either with
-@option{-msse}, or with a combination of @option{-m3dnow} and
-@option{-march=athlon}. All of them generate the machine
-instruction that is part of the name.
+@option{-msse}, or with @option{-m3dnowa}. All of them generate
+the machine instruction that is part of the name.
@smallexample
v4hi __builtin_ia32_pmulhuw (v4hi, v4hi)
v4hi __builtin_ia32_pmulhrw (v4hi, v4hi)
@end smallexample
-The following built-in functions are available when both @option{-m3dnow}
-and @option{-march=athlon} are used. All of them generate the machine
-instruction that is part of the name.
+The following built-in functions are available when @option{-m3dnowa} is used.
+All of them generate the machine instruction that is part of the name.
@smallexample
v2si __builtin_ia32_pf2iw (v2sf)
-mavx512bw -mavx512dq -mavx512ifma -mavx512vbmi -msha -maes @gol
-mpclmul -mfsgsbase -mrdrnd -mf16c -mfma @gol
-mprefetchwt1 -mclflushopt -mxsavec -mxsaves @gol
--msse4a -m3dnow -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop -mlzcnt @gol
--mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx -mmwaitx @gol
--mclzero -mpku -mthreads @gol
+-msse4a -m3dnow -m3dnowa -mpopcnt -mabm -mbmi -mtbm -mfma4 -mxop @gol
+-mlzcnt -mbmi2 -mfxsr -mxsave -mxsaveopt -mrtm -mlwp -mmpx @gol
+-mmwaitx -mclzero -mpku -mthreads @gol
-mms-bitfields -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mmemcpy-strategy=@var{strategy} -mmemset-strategy=@var{strategy} @gol
@itemx -m3dnow
@opindex m3dnow
@need 200
+@itemx -m3dnowa
+@opindex m3dnowa
+@need 200
@itemx -mpopcnt
@opindex mpopcnt
@need 200
SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, AVX512CD,
SHA, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM,
AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA AVX512VBMI, BMI, BMI2, FXSR,
-XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU or 3DNow!@:
+XSAVE, XSAVEOPT, LZCNT, RTM, MPX, MWAITX, PKU, 3DNow!@: or enhanced 3DNow!@:
extended instruction sets. Each has a corresponding @option{-mno-} option
to disable use of these instructions.
2017-02-18 Jakub Jelinek <jakub@redhat.com>
+ PR target/79569
+ * gcc.target/i386/3dnowA-3.c: New test.
+
PR target/79559
* gcc.target/i386/pr79559.c: New test.
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -m3dnowa" } */
+
+#include <mm3dnow.h>
+
+__m64
+foo (__m64 x, __m64 y)
+{
+ return _m_pfnacc (x, y);
+}