};
def macroop FSTP_M {
- movfp ufp1, st(0), spm=1
+ movfp ufp1, st(0)
stfp ufp1, seg, sib, disp
+ pop87
};
def macroop FSTP_P {
- movfp ufp1, st(0), spm=1
+ movfp ufp1, st(0)
rdip t7
stfp ufp1, seg, riprel, disp
+ pop87
};
'''
class chsfp(FpUnaryOp):
code = 'FpDestReg = (-1) * (FpSrcReg1);'
flag_code = 'FSW = FSW & (~CC1Bit);'
+
+ class Pop87(FpUnaryOp):
+ def __init__(self, spm=1, UpdateFTW=True):
+ super(Pop87, self).__init__( \
+ "InstRegIndex(FLOATREG_MICROFP0)", \
+ "InstRegIndex(FLOATREG_MICROFP0)", \
+ spm=spm, SetStatus=False, UpdateFTW=UpdateFTW)
+
+ code = ''
}};