r600: use the drm ioctls for swap and texture upload
authorAlex Deucher <alexdeucher@gmail.com>
Wed, 12 Aug 2009 02:15:18 +0000 (22:15 -0400)
committerAlex Deucher <alexdeucher@gmail.com>
Wed, 12 Aug 2009 02:21:26 +0000 (22:21 -0400)
NOTE:  THIS REQUIRES AN UPDATED DRM!

src/mesa/drivers/dri/radeon/radeon_bo_legacy.c
src/mesa/drivers/dri/radeon/radeon_common.c

index 8c19f30106506a389ac090feee9075b81bd01bde..6d6ae5d3b2fc70f2d17fa2350bb078f8e15d28a7 100644 (file)
@@ -624,12 +624,34 @@ static int bo_vram_validate(struct radeon_bo *bo,
 
     if (bo_legacy->dirty || bo_legacy->tobj->base.dirty_images[0]) {
            if (IS_R600_CLASS(boml->screen)) {
-                   char *src = bo_legacy->ptr;
-                   char *dst = (char *) boml->screen->driScreen->pFB +
-                           (bo_legacy->offset - boml->fb_location);
+                   drm_radeon_texture_t tex;
+                   drm_radeon_tex_image_t tmp;
+                   int ret;
+
+                   tex.offset = bo_legacy->offset;
+                   tex.image = &tmp;
+                   assert(!(tex.offset & 1023));
 
-                   /* FIXME: alignment, pitch, etc. */
-                   memcpy(dst, src, bo->size);
+                   tmp.x = 0;
+                   tmp.y = 0;
+                   tmp.width = bo->size;
+                   tmp.height = 1;
+                   tmp.data = bo_legacy->ptr;
+                   tex.format = RADEON_TXFORMAT_ARGB8888;
+                   tex.width = tmp.width;
+                   tex.height = tmp.height;
+                   tex.pitch = bo->size;
+                   do {
+                           ret = drmCommandWriteRead(bo->bom->fd,
+                                                     DRM_RADEON_TEXTURE,
+                                                     &tex,
+                                                     sizeof(drm_radeon_texture_t));
+                           if (ret) {
+                                   if (RADEON_DEBUG & DEBUG_IOCTL)
+                                           fprintf(stderr, "DRM_RADEON_TEXTURE:  again!\n");
+                                   usleep(1);
+                           }
+                   } while (ret == -EAGAIN);
            } else {
                    /* Copy to VRAM using a blit.
                     * All memory is 4K aligned. We're using 1024 pixels wide blits.
index 39f19933329c57dccde547fcfc06fb6f6dcfbcc8..330c2c8a86e2bcd1e1d4ec21f1e7888b1d7d79cf 100644 (file)
@@ -481,32 +481,6 @@ void radeonCopyBuffer( __DRIdrawablePrivate *dPriv,
                if (!n)
                        continue;
 
-               if (IS_R600_CLASS(rmesa->radeonScreen)) {
-                       int cpp = rmesa->radeonScreen->cpp;
-                       int src_pitch = rmesa->radeonScreen->backPitch * cpp;
-                       int dst_pitch = rmesa->radeonScreen->frontPitch * cpp;
-                       char *src = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->backOffset;
-                       char *dst = (char *)rmesa->radeonScreen->driScreen->pFB + rmesa->radeonScreen->frontOffset;
-                       int j;
-                       drm_clip_rect_t *pb = rmesa->sarea->boxes;
-
-                       for (j = 0; j < n; j++) {
-                               int x = pb[j].x1;
-                               int y = pb[j].y1;
-                               int w = pb[j].x2 - x;
-                               int h = pb[j].y2 - y;
-
-                               src += (y * src_pitch) + (x * cpp);
-                               dst += (y * dst_pitch) + (x * cpp);
-
-                               while (h--) {
-                                       memcpy(dst, src, w * cpp);
-                                       src += src_pitch;
-                                       dst += dst_pitch;
-                               }
-                       }
-               }
-
                ret = drmCommandNone( rmesa->dri.fd, DRM_RADEON_SWAP );
 
                if ( ret ) {