fix fcvttg FPSCR.FR computation

the unit test previously assumed the rounding mode is truncate,
but when I switched it to allow dynamic rounding modes,
I forgot to no longer hard-code FPSCR.FR = 0

diff --git a/openpower/isa/fpcvt.mdwn b/openpower/isa/fpcvt.mdwn
index 0d2b859f245e731ec18788b8c151699cdc13f791..d14dec91611fe716ff97a102c2437cd8ac25a285 100644 (file)
--- a/openpower/isa/fpcvt.mdwn
+++ b/openpower/isa/fpcvt.mdwn
@@ -192,8 +192,10 @@ Pseudo-code:
         overflow <- 1  # signals SO only when OE = 1
         vxcvi_flag <- 1
         xx_flag <- 0
-    else if ¬bfp_COMPARE_EQ(src, result_bfp) then
-        xx_flag <- 1
+        inc_flag <- 0
+    else
+        xx_flag <- ¬bfp_COMPARE_EQ(src, result_bfp)
+        inc_flag <- bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
     if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
     if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
     if xx_flag = 1 then SetFX(FPSCR.XX)
@@ -307,8 +309,10 @@ Pseudo-code:
         overflow <- 1  # signals SO only when OE = 1
         vxcvi_flag <- 1
         xx_flag <- 0
-    else if ¬bfp_COMPARE_EQ(src, result_bfp) then
-        xx_flag <- 1
+        inc_flag <- 0
+    else
+        xx_flag <- ¬bfp_COMPARE_EQ(src, result_bfp)
+        inc_flag <- bfp_COMPARE_GT(bfp_ABSOLUTE(result_bfp), bfp_ABSOLUTE(src))
     if vxsnan_flag = 1 then SetFX(FPSCR.VXSNAN)
     if vxcvi_flag = 1 then SetFX(FPSCR.VXCVI)
     if xx_flag = 1 then SetFX(FPSCR.XX)

diff --git a/src/openpower/test/fmv_fcvt/fmv_fcvt.py b/src/openpower/test/fmv_fcvt/fmv_fcvt.py
index 524edce1233124f4e0941b6c8d44de1bf7096c83..d47f35ccf5ef7839db59af3e8c2634876fc655e1 100644 (file)
--- a/src/openpower/test/fmv_fcvt/fmv_fcvt.py
+++ b/src/openpower/test/fmv_fcvt/fmv_fcvt.py
@@ -125,7 +125,8 @@ class FMvFCvtCases(TestAccumulatorBase):
                 fpscr.FX = 1
                 fpscr.FI = 1
             fpscr.FPRF = 0  # undefined value we happen to pick
-            fpscr.FR = 0  # trunc never increments
+            if not overflow:
+                fpscr.FR = abs(do_round(inp, round_mode)) > abs(inp)
             lt = bool(expected & (1 << 63))
             gt = not lt and expected != 0
             eq = expected == 0