clarify that LR/SC are not to be parallelised

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 9f0e3536b36028340907472cb0e793180db93f53..5ca1952084afb3505b0e52e948d9e27e1de4ec22 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -331,7 +331,10 @@ instructions are added to any given RV extension, their functionality
 will be inherently parallelised.
 
 CSR instructions, LUI, C.J, C.JR, WFI, AUIPC are not suitable for parallelising
-so are left as scalar.  EBREAK, NOP, FENCE and others do not use registers
+so are left as scalar.  LR/SC could hypothetically be parallelised
+however their purpose is single (complex) atomic memory operations, and
+it would be unwise to attempt to parallelise them.
+EBREAK, NOP, FENCE and others do not use registers
 so are not inherently paralleliseable either.  All other operations using
 registers are automatically parallelised.