(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index d4b56e37a898dd135215db7632fccbe25462a258..fa883fc98992c63c39b8a493dc01ce8c6a009016 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -41,12 +41,19 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | MASK                         | `1:3`      | Execution Mask                                                            |
 | ELWIDTH                      | `4:5`      | Element Width                                                             |
 | SUBVL                        | `6:7`      | Sub-vector length                                                         |
-| Rdest_EXTRA                  | `8:10`     | extra bits for Rdest (Uses R\*_EXTRA Encoding)                            |
-| Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
-| Rsrc2_EXTRA                  | `14:16`    | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding)                            |
-| Rsrc3_EXTRA                  | `17:18`    | extra bits for Rsrc3 (Uses 2-bit R\*_EXTRA Encoding)                            |
 | MODE                          | `19:23`    | see [[discussion]]                                                                      |
 
+| Rdest_EXTRA2 | `8:9`   | extra bits for Rdest (R\*_EXTRA2 Encoding)        |
+| Rsrc1_EXTRA2 | `10:11` | extra bits for Rsrc1 (R\*_EXTRA2 Encoding)        |
+| Rsrc2_EXTRA2 | `12:13` | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding)                            |
+| Rsrc3_EXTRA2 | `14:15` | extra bits for Rsrc3 (Uses 2-bit R\*_EXTRA Encoding)                            |
+| reserved     | `16`   | extra bits for Rsrc3 (Uses 2-bit R\*_EXTRA Encoding)
+
+| Rdest_EXTRA3                  | `8:10`     | extra bits for Rdest (Uses R\*_EXTRA Encoding)                            |
+| Rsrc1_EXTRA3                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
+| Rsrc2_EXTRA3                  | `14:16`    | extra bits for Rsrc2 (Uses R\*_EXTRA Encoding)                            |
+                            |
+
 ### Twin Predication (src=1, dest=1)
 
 | Remapped Encoding Field Name | Field bits | Description                                                               |
@@ -55,8 +62,8 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 | MASK                         | `1:3`      | Execution Mask                                                            |
 | ELWIDTH                      | `4:5`      | Element Width                                                             |
 | SUBVL                        | `6:7`      | Sub-vector length                                                         |
-| Rdest_EXTRA                  | `8:10`     | extra bits for Rdest (Uses R\*_EXTRA Encoding)                            |
-| Rsrc1_EXTRA                  | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
+| Rdest_EXTRA3                 | `8:10`     | extra bits for Rdest (Uses R\*_EXTRA Encoding)                            |
+| Rsrc1_EXTRA3                 | `11:13`    | extra bits for Rsrc1 (Uses R\*_EXTRA Encoding)                            |
 | MASK_SRC                     | `14:16`    | Execution Mask for Source (only on instructions with twin-predication)    |
 | ELWIDTH_SRC                  | `17:18`    | Element Width for Source (only on instructions with twin-predication)     |
 | MODE                          | `19:23`    | see [[discussion]]                                                                       |