x86: Add stats to X86 TLB

Change-Id: Iebf7d245de66eebc8d4c59e62e52adf6cf51e1e4
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3980
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 191e91a004a521cccafe81f91520fa5b6eec65ef..e954c9c738d7a5642a5eea954d8089ee51c3eb60 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -332,7 +332,20 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             DPRINTF(TLB, "Paging enabled.\n");
             // The vaddr already has the segment base applied.
             TlbEntry *entry = lookup(vaddr);
+            if (mode == Read) {
+                rdAccesses++;
+            } else {
+                wrAccesses++;
+            }
             if (!entry) {
+                DPRINTF(TLB, "Handling a TLB miss for "
+                        "address %#x at pc %#x.\n",
+                        vaddr, tc->instAddr());
+                if (mode == Read) {
+                    rdMisses++;
+                } else {
+                    wrMisses++;
+                }
                 if (FullSystem) {
                     Fault fault = walker->start(tc, translation, req, mode);
                     if (timing || fault != NoFault) {
@@ -343,10 +356,6 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
                     entry = lookup(vaddr);
                     assert(entry);
                 } else {
-                    DPRINTF(TLB, "Handling a TLB miss for "
-                            "address %#x at pc %#x.\n",
-                            vaddr, tc->instAddr());
-
                     Process *p = tc->getProcessPtr();
                     TlbEntry newEntry;
                     bool success = p->pTable->lookup(vaddr, newEntry);
@@ -444,6 +453,29 @@ TLB::getWalker()
     return walker;
 }
 
+void
+TLB::regStats()
+{
+    using namespace Stats;
+
+    rdAccesses
+        .name(name() + ".rdAccesses")
+        .desc("TLB accesses on read requests");
+
+    wrAccesses
+        .name(name() + ".wrAccesses")
+        .desc("TLB accesses on write requests");
+
+    rdMisses
+        .name(name() + ".rdMisses")
+        .desc("TLB misses on read requests");
+
+    wrMisses
+        .name(name() + ".wrMisses")
+        .desc("TLB misses on write requests");
+
+}
+
 void
 TLB::serialize(CheckpointOut &cp) const
 {

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index a134ad4275d40123593b51b8975d7f89b2561bf0..09cd6edc7398cd81c5a31cbd0ad7e0d369b1a5f4 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -100,6 +100,12 @@ namespace X86ISA
         TlbEntryTrie trie;
         uint64_t lruSeq;
 
+        // Statistics
+        Stats::Scalar rdAccesses;
+        Stats::Scalar wrAccesses;
+        Stats::Scalar rdMisses;
+        Stats::Scalar wrMisses;
+
         Fault translateInt(RequestPtr req, ThreadContext *tc);
 
         Fault translate(RequestPtr req, ThreadContext *tc,
@@ -142,6 +148,11 @@ namespace X86ISA
 
         TlbEntry * insert(Addr vpn, TlbEntry &entry);
 
+        /*
+         * Function to register Stats
+         */
+        void regStats();
+
         // Checkpointing
         void serialize(CheckpointOut &cp) const override;
         void unserialize(CheckpointIn &cp) override;