boards/plarforms/genesys2: replace user_dip_sw with user_sw

diff --git a/litex/boards/platforms/genesys2.py b/litex/boards/platforms/genesys2.py
index f5d5a25cca842e2d6f91e7e0f70b559ef1ec4c0b..e8d8fc3bb5e6468f6a61a64be9dddfb45365ee37 100644 (file)
--- a/litex/boards/platforms/genesys2.py
+++ b/litex/boards/platforms/genesys2.py
@@ -20,14 +20,14 @@ _io = [
     ("user_btn_r", 0, Pins("C19"), IOStandard("LVCMOS33")),
     ("user_btn_u", 0, Pins("B19"), IOStandard("LVCMOS33")),
 
-    ("user_dip_sw", 0, Pins("G19"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 1, Pins("G25"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 2, Pins("H24"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 3, Pins("K19"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 4, Pins("N19"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 5, Pins("P19"), IOStandard("LVCMOS12")),
-    ("user_dip_sw", 6, Pins("P26"), IOStandard("LVCMOS33")),
-    ("user_dip_sw", 7, Pins("P27"), IOStandard("LVCMOS33")),
+    ("user_sw", 0, Pins("G19"), IOStandard("LVCMOS12")),
+    ("user_sw", 1, Pins("G25"), IOStandard("LVCMOS12")),
+    ("user_sw", 2, Pins("H24"), IOStandard("LVCMOS12")),
+    ("user_sw", 3, Pins("K19"), IOStandard("LVCMOS12")),
+    ("user_sw", 4, Pins("N19"), IOStandard("LVCMOS12")),
+    ("user_sw", 5, Pins("P19"), IOStandard("LVCMOS12")),
+    ("user_sw", 6, Pins("P26"), IOStandard("LVCMOS33")),
+    ("user_sw", 7, Pins("P27"), IOStandard("LVCMOS33")),
 
     ("clk200", 0,
         Subsignal("p", Pins("AD12"), IOStandard("LVDS")),