partially fix FPCSR in "Special Registers altered" sections

didn't yet fill in "TODO: which bits?"

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 026474a9ecde78ade76b0081646803fd81cae0fb..50d0dccae930aabefdb46fc04dacadb334eaf736 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -271,7 +271,7 @@ operations.
 Special Registers altered:
 
     CR1     (if Rc=1)
-    FPCSR   (TODO: which bits?)
+    FPCSR   (TODO: which bits?) (if IT[0] != 0 or RCS[0] != 0)
 
 ### Assembly Aliases
 
@@ -574,6 +574,7 @@ Special Registers altered:
 
     CR0              (if Rc=1)
     XER SO, OV, OV32 (if OE=1)
+    FPCSR   (TODO: which bits?)
 
 ----------