xilinx_dsp to be sensitive to keep attribute

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index 1a3dcdcbb11106be4803b0a45d4fe8f0dc0f30de..7f1958d5d4a41ecb37baa531165ae1238519e963 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -29,8 +29,13 @@ match ffA
 endmatch
 
 code clock
-       if (ffA)
+       if (ffA) {
                clock = port(ffA, \CLK).as_bit();
+
+               for (auto b : port(ffA, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
+       }
 endcode
 
 match ffB
@@ -45,6 +50,10 @@ endmatch
 
 code clock
        if (ffB) {
+               for (auto b : port(ffB, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
+
                SigBit c = port(ffB, \CLK).as_bit();
 
                if (clock != SigBit() && c != clock)
@@ -156,6 +165,10 @@ code ffP clock
 //             ffP = ffY;
 
        if (ffP) {
+               for (auto b : port(ffP, \Q))
+                       if (b.wire->get_bool_attribute(\keep))
+                               reject;
+
                SigBit c = port(ffP, \CLK).as_bit();
 
                if (clock != SigBit() && c != clock)