Make tests/aiger less chatty

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/tests/aiger/run-test.sh b/tests/aiger/run-test.sh
index f52eb4ac1a8de7df2fc0b8b63bb6b051a5a02f1a..5246c1b489186ce2fe250aaa35284d233a7cc1bb 100755 (executable)
--- a/tests/aiger/run-test.sh
+++ b/tests/aiger/run-test.sh
@@ -10,8 +10,9 @@ for aag in *.aag; do
     # Since ABC cannot read *.aag, read the *.aig instead
     # (which would have been created by the reference aig2aig utility,
     #  available from http://fmv.jku.at/aiger/)
-    ../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
-    ../../yosys -p "
+    echo "Checking $aag."
+    ../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
+    ../../yosys -qp "
 read_verilog ${aag%.*}_ref.v
 prep
 design -stash gold
@@ -26,8 +27,9 @@ sat -verify -prove-asserts -show-ports -seq 16 miter
 done
 
 for aig in *.aig; do
-    ../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
-    ../../yosys -p "
+    echo "Checking $aig."
+    ../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
+    ../../yosys -qp "
 read_verilog ${aig%.*}_ref.v
 prep
 design -stash gold