Fix extraction from odd-numbered MSA registers

This fixes a build-failure with gcc.c-torture/execute/20050604-1.c when
using -mabi=32 -mmsa -mno-odd-spreg.

gcc/
	* config/mips/mips-msa.md (msa_vec_extract_<msafmt_f>): Update
	extraction from odd-numbered MSA register.

From-SVN: r246613

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ba4f7fd0dbb937d2e117f628b40c3cbdd64515cb..594b32a4563db4e5175e2bdca8a00c9677ce482c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-03-31  Matthew Fortune  <matthew.fortune@imgtec.com>
+
+       * config/mips/mips-msa.md (msa_vec_extract_<msafmt_f>): Update
+       extraction from odd-numbered MSA register.
+
 2017-03-31  Jakub Jelinek  <jakub@redhat.com>
 
        PR middle-end/80173

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index accb8de387ca1ee2e8e5822dbf671a34eed57133..c80be471026cfedf3e4b0870460895b8200752aa 100644 (file)
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -366,7 +366,20 @@
   "#"
   "&& reload_completed"
   [(set (match_dup 0) (match_dup 1))]
-  "operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));"
+{
+  /* An MSA register cannot be reinterpreted as a single precision
+     register when using -mno-odd-spreg and the MSA register is
+     an odd number.  */
+  if (<UNITMODE>mode == SFmode && !TARGET_ODD_SPREG
+      && (REGNO (operands[1]) & 1))
+    {
+      emit_move_insn (gen_rtx_REG (<MODE>mode, REGNO (operands[0])),
+                     operands[1]);
+      operands[1] = operands[0];
+    }
+  else
+    operands[1] = gen_rtx_REG (<UNITMODE>mode, REGNO (operands[1]));
+}
   [(set_attr "move_type" "fmove")
    (set_attr "mode" "<UNITMODE>")])