Force $inout.out ports to begin with '$' to indicate internal

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index cbce4c83b39eba32d3388d4cc8df42e82baf10ea..21b281708f92a98c2d2787a46e30ea84e3615784 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -424,7 +424,7 @@ struct XAigerWriter
                        // inherit existing inout's drivers
                        if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
                                        || keep_bits.count(bit)) {
-                               RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
+                               RTLIL::IdString wire_name = stringf("$%s$inout.out", wire->name.c_str());
                                RTLIL::Wire *new_wire = module->wire(wire_name);
                                if (!new_wire)
                                        new_wire = module->addWire(wire_name, GetSize(wire));

diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc
index e8ee487e50e36381f0e62346fbb7eac9bec0906c..986d34fb3445980a1f8d6e7530a7f7d33b9e95cb 100644 (file)
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@ -868,7 +868,7 @@ void AigerReader::post_process()
                                        if (!existing) {
                                                if (escaped_s.ends_with("$inout.out")) {
                                                        wire->port_output = false;
-                                                       RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
+                                                       RTLIL::Wire *in_wire = module->wire(escaped_s.substr(1, escaped_s.size()-11));
                                                        log_assert(in_wire);
                                                        log_assert(in_wire->port_input && !in_wire->port_output);
                                                        in_wire->port_output = true;
@@ -889,7 +889,7 @@ void AigerReader::post_process()
                                        if (!existing) {
                                                if (escaped_s.ends_with("$inout.out")) {
                                                        wire->port_output = false;
-                                                       RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
+                                                       RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(1, escaped_s.size()-11).c_str(), index));
                                                        log_assert(in_wire);
                                                        log_assert(in_wire->port_input && !in_wire->port_output);
                                                        in_wire->port_output = true;