soc/cores/cpu/minerva: add self.reset to i_rst

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index b353dcae0b3925db980c86031716f56de38bcd9c..9cac00d8c776b9567529e27cf13213cd42100949 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -48,7 +48,7 @@ class Minerva(CPU):
         self.cpu_params = dict(
             # clock / reset
             i_clk=ClockSignal(),
-            i_rst=ResetSignal(),
+            i_rst=ResetSignal() | self.reset,
 
             # interrupts
             i_timer_interrupt    = 0,