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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 0acb474d596480852427a5a80fbdaec7aa4c6750..20cd6a83692dc7f95121fbeee333e6ec66f26b09 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -890,10 +890,13 @@ directly themselves.
 However the source code and binary would be near-identical if
 not identical in every respect, and the PEs implementing the full
 ZOLC capability in order to compact binary size to the bare minimum.
+The main CPU's role would be to coordinate and manage the PEs
+over OpenCAPI.
 
 One key strategic question does remain: do the PEs need to have
 a RADIX MMU and associated TLB-aware minimal L1 Cache, in order
-to support OpenCAPI properly? The saving grace here is that with
+to support OpenCAPI properly? The answer is very likely to be yes.
+The saving grace here is that with
 the expectation of running only hot-loops with ZOLC-driven
 binaries, the size of L1 Cache needed would be miniscule compared
 to the average high-end CPU.