(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 90d689ca6d30a11ab44a8b8b29fb983652f0ae36..45e325dd7a590dc9d45e7eac93f47b3d5720ad53 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -11,7 +11,14 @@ SVP64 is designed around these fundamental and inviolate principles:
 3. A hardware-level for-loop makes vector elements 100% synonymous
    with scalar instructions (the suffix)
 
-That said, there are a few exceptional places where these rules get
+How can a Vector ISA even exist when no actual Vector instructions
+are permitted to be added? It comes down to the strict abstraction.
+First you add a **scalar** instruction (32-bit). Second, the
+Prefixing is applied *in the abstract* to give the *appearance*
+and ultimately the same effect as if an explicit Vector instruction
+had also been added.
+
+There are a few exceptional places where these rules get
 bent, and others where the rules take some explaining,
 and this page tracks them.