RISCV_GCC = riscv-gcc
RISCV_GCC_OPTS = -nostdlib -nostartfiles -Wa,-march=RVIMAFDXhwacha
RISCV_OBJDUMP = riscv-objdump --disassemble-all --section=.text --section=.data --section=.bss
-RISCV_SIM = spike
+RISCV_SIM = spike --extension=hwacha
vpath %.S $(isa_src_dir)
rv64uf_pt_vec_tests = $(addprefix rv64uf-pt-vec-, $(rv64uf_sc_vec_tests))
rv64uf_v_vec_tests = $(addprefix rv64uf-v-vec-, $(rv64uf_sc_vec_tests))
-spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) #$(rv64uf_p_vec_tests) $(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
+spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) $(rv64uf_p_vec_tests) #$(rv64uf_pt_vec_tests) $(rv64uf_v_vec_tests)
rv64ui_pt_vec_tests = $(addprefix rv64ui-pt-vec-, $(rv64ui_sc_vec_tests))
rv64ui_v_vec_tests = $(addprefix rv64ui-v-vec-, $(rv64ui_sc_vec_tests))
-spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) #$(rv64ui_p_vec_tests) $(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
+spike_tests += $(rv64ui_p_tests) $(rv64ui_pm_tests) $(rv64ui_v_tests) $(rv64ui_p_vec_tests) #$(rv64ui_pt_vec_tests) $(rv64ui_v_vec_tests)
fmovn fmovz \
vvadd_d vvadd_w vvadd_fd vvadd_fw \
vvmul_d \
- vvadd_branch \
rv64uv_sc_vec_tests = \
beq bge bgeu blt bltu bne \
rv64uv_pt_vec_tests = $(addprefix rv64uv-pt-vec-, $(rv64uv_sc_vec_tests))
rv64uv_v_vec_tests = $(addprefix rv64uv-v-vec-, $(rv64uv_sc_vec_tests))
-spike_tests += #$(rv64uv_p_tests)
+spike_tests += $(rv64uv_p_tests)