Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec...

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+In-Reply-To: <ba6dfcfcac4cb37dab95ba1669f68f57f01347d1.camel@ozlabs.org>
+From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+Date: Wed, 13 May 2020 10:11:44 +0100
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+Message-ID: <CAPweEDxRW3EsvLjn1fUZzriBx34YFDFBLPYuGrO6h8-nJVWKvg@mail.gmail.com>
+To: Benjamin Herrenschmidt <benh@ozlabs.org>
+Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only
+ power cores and spec compliance
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