---------- Begin Simulation Statistics ----------
-host_inst_rate 1902681 # Simulator instruction rate (inst/s)
-host_mem_usage 378772 # Number of bytes of host memory used
-host_seconds 26.70 # Real time elapsed on the host
-host_tick_rate 964308738 # Simulator tick rate (ticks/s)
+host_inst_rate 1831927 # Simulator instruction rate (inst/s)
+host_mem_usage 384484 # Number of bytes of host memory used
+host_seconds 27.81 # Real time elapsed on the host
+host_tick_rate 928414614 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 50805202 # Number of instructions simulated
-sim_seconds 0.025749 # Number of seconds simulated
-sim_ticks 25749159000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 96510 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 96510 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits::0 91456 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 91456 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052368 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5054 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5054 # number of LoadLockedReq misses
-system.cpu.dcache.ReadReq_accesses::0 7686910 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7686910 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_hits::0 7455461 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7455461 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_rate::0 0.030109 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 231449 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 231449 # number of ReadReq misses
-system.cpu.dcache.StoreCondReq_accesses::0 96509 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 96509 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 96509 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 96509 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6583516 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6583516 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 6409119 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6409119 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.026490 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 174397 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 174397 # number of WriteReq misses
+sim_insts 50949504 # Number of instructions simulated
+sim_seconds 0.025821 # Number of seconds simulated
+sim_ticks 25821310500 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0 96794 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 96794 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits::0 91895 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 91895 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.050613 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 4899 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 4899 # number of LoadLockedReq misses
+system.cpu.dcache.ReadReq_accesses::0 7714516 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7714516 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_hits::0 7482193 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7482193 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_rate::0 0.030115 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 232323 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 232323 # number of ReadReq misses
+system.cpu.dcache.StoreCondReq_accesses::0 96793 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 96793 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 96793 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 96793 # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0 6604860 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6604860 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_hits::0 6433311 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6433311 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_rate::0 0.025973 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 171549 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 171549 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 34.349377 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 34.663994 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 14270426 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 14319376 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 14270426 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 14319376 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13864580 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 13915504 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13864580 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13915504 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.028440 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0 0.028205 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 405846 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 403872 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 405846 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 403872 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999474 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.730497 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 14270426 # number of overall (read+write) accesses
+system.cpu.dcache.occ_%::0 0.999475 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 511.731250 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0 14319376 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 14270426 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 14319376 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13864580 # number of overall hits
+system.cpu.dcache.overall_hits::0 13915504 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13864580 # number of overall hits
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system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.028440 # miss rate for overall accesses
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 405846 # number of overall misses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 405846 # number of overall misses
+system.cpu.dcache.overall_misses::total 403872 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 408645 # number of replacements
-system.cpu.dcache.sampled_refs 409157 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 406424 # number of replacements
+system.cpu.dcache.sampled_refs 406936 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.730497 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14054288 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 511.731250 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14106027 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 21760000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 380684 # number of writebacks
-system.cpu.dtb.accesses 15287038 # DTB accesses
+system.cpu.dcache.writebacks 379025 # number of writebacks
+system.cpu.dtb.accesses 15336291 # DTB accesses
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.flush_entries 2258 # Number of entries that have been flushed from TLB
+system.cpu.dtb.flush_entries 2242 # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.hits 15281544 # DTB hits
+system.cpu.dtb.hits 15330762 # DTB hits
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.misses 5494 # DTB misses
+system.cpu.dtb.misses 5529 # DTB misses
system.cpu.dtb.perms_faults 255 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.prefetch_faults 771 # Number of TLB faults due to prefetch
-system.cpu.dtb.read_accesses 8595265 # DTB read accesses
-system.cpu.dtb.read_hits 8590763 # DTB read hits
-system.cpu.dtb.read_misses 4502 # DTB read misses
-system.cpu.dtb.write_accesses 6691773 # DTB write accesses
-system.cpu.dtb.write_hits 6690781 # DTB write hits
-system.cpu.dtb.write_misses 992 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 41062986 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 41062986 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_hits::0 40634897 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 40634897 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_rate::0 0.010425 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 428089 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 428089 # number of ReadReq misses
+system.cpu.dtb.prefetch_faults 768 # Number of TLB faults due to prefetch
+system.cpu.dtb.read_accesses 8622893 # DTB read accesses
+system.cpu.dtb.read_hits 8618361 # DTB read hits
+system.cpu.dtb.read_misses 4532 # DTB read misses
+system.cpu.dtb.write_accesses 6713398 # DTB write accesses
+system.cpu.dtb.write_hits 6712401 # DTB write hits
+system.cpu.dtb.write_misses 997 # DTB write misses
+system.cpu.icache.ReadReq_accesses::0 41172623 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_hits::0 40741841 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 40741841 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_rate::0 0.010463 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 430782 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 430782 # number of ReadReq misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 94.921831 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 94.576690 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 41062986 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 41062986 # number of demand (read+write) accesses
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system.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 40634897 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 40634897 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.010425 # miss rate for demand accesses
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 428089 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 428089 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.928964 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 475.629536 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 41062986 # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0 0.929162 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 41062986 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 40634897 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 40634897 # number of overall hits
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system.cpu.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.010425 # miss rate for overall accesses
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 428089 # number of overall misses
+system.cpu.icache.overall_misses::total 430782 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 427576 # number of replacements
-system.cpu.icache.sampled_refs 428088 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 430269 # number of replacements
+system.cpu.icache.sampled_refs 430781 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 475.629536 # Cycle average of tags in use
-system.cpu.icache.total_refs 40634897 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 475.731149 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 4544230000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 30587 # number of writebacks
+system.cpu.icache.writebacks 33727 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
-system.cpu.itb.accesses 41064113 # DTB accesses
+system.cpu.itb.accesses 41173750 # DTB accesses
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries 1478 # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb_asid 40 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 33670 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.hits 41061294 # DTB hits
-system.cpu.itb.inst_accesses 41064113 # ITB inst accesses
-system.cpu.itb.inst_hits 41061294 # ITB inst hits
-system.cpu.itb.inst_misses 2819 # ITB inst misses
-system.cpu.itb.misses 2819 # DTB misses
+system.cpu.itb.hits 41170928 # DTB hits
+system.cpu.itb.inst_accesses 41173750 # ITB inst accesses
+system.cpu.itb.inst_hits 41170928 # ITB inst hits
+system.cpu.itb.inst_misses 2822 # ITB inst misses
+system.cpu.itb.misses 2822 # DTB misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 51498319 # number of cpu cycles simulated
-system.cpu.num_insts 50805202 # Number of instructions executed
-system.cpu.num_refs 16039990 # Number of memory references
+system.cpu.numCycles 51642622 # number of cpu cycles simulated
+system.cpu.num_insts 50949504 # Number of instructions executed
+system.cpu.num_refs 16092645 # Number of memory references
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
-system.l2c.ReadExReq_accesses::0 172654 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 172654 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_hits::0 63568 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 63568 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_rate::0 0.631819 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 109086 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 109086 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 662584 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 6745 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 669329 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 644874 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 6723 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 651597 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.026729 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.003262 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.029990 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 17710 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 22 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 17732 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 1743 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1743 # number of UpgradeReq accesses(hits+misses)
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+system.l2c.ReadExReq_hits::0 60310 # number of ReadExReq hits
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+system.l2c.ReadExReq_miss_rate::0 0.644637 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 109404 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 109404 # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0 665898 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 6073 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_miss_rate::1 0.003952 # miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_accesses::0 1835 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_rate::0 0.990247 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1726 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1726 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 411271 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 411271 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 411271 # number of Writeback hits
-system.l2c.Writeback_hits::total 411271 # number of Writeback hits
+system.l2c.UpgradeReq_miss_rate::0 0.990736 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1818 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1818 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 412752 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 412752 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 412752 # number of Writeback hits
+system.l2c.Writeback_hits::total 412752 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.881395 # Average number of references to valid blocks.
+system.l2c.avg_refs 6.885433 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 835238 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 6745 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 841983 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 835612 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 6073 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 841685 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 708442 # number of demand (read+write) hits
-system.l2c.demand_hits::1 6723 # number of demand (read+write) hits
-system.l2c.demand_hits::total 715165 # number of demand (read+write) hits
+system.l2c.demand_hits::0 708536 # number of demand (read+write) hits
+system.l2c.demand_hits::1 6049 # number of demand (read+write) hits
+system.l2c.demand_hits::total 714585 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.151808 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.003262 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.155070 # miss rate for demand accesses
-system.l2c.demand_misses::0 126796 # number of demand (read+write) misses
-system.l2c.demand_misses::1 22 # number of demand (read+write) misses
-system.l2c.demand_misses::total 126818 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::0 0.152075 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.003952 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.156027 # miss rate for demand accesses
+system.l2c.demand_misses::0 127076 # number of demand (read+write) misses
+system.l2c.demand_misses::1 24 # number of demand (read+write) misses
+system.l2c.demand_misses::total 127100 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.072867 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.479441 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 4775.385687 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31420.668700 # Average occupied blocks per context
-system.l2c.overall_accesses::0 835238 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 6745 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 841983 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.072507 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.478199 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 4751.792305 # Average occupied blocks per context
+system.l2c.occ_blocks::1 31339.221407 # Average occupied blocks per context
+system.l2c.overall_accesses::0 835612 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 6073 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 841685 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 708442 # number of overall hits
-system.l2c.overall_hits::1 6723 # number of overall hits
-system.l2c.overall_hits::total 715165 # number of overall hits
+system.l2c.overall_hits::0 708536 # number of overall hits
+system.l2c.overall_hits::1 6049 # number of overall hits
+system.l2c.overall_hits::total 714585 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.151808 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.003262 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.155070 # miss rate for overall accesses
-system.l2c.overall_misses::0 126796 # number of overall misses
-system.l2c.overall_misses::1 22 # number of overall misses
-system.l2c.overall_misses::total 126818 # number of overall misses
+system.l2c.overall_miss_rate::0 0.152075 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.003952 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.156027 # miss rate for overall accesses
+system.l2c.overall_misses::0 127076 # number of overall misses
+system.l2c.overall_misses::1 24 # number of overall misses
+system.l2c.overall_misses::total 127100 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 94668 # number of replacements
-system.l2c.sampled_refs 125475 # Sample count of references to valid blocks.
+system.l2c.replacements 95922 # number of replacements
+system.l2c.sampled_refs 125830 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 36196.054387 # Cycle average of tags in use
-system.l2c.total_refs 863443 # Total number of references to valid blocks.
+system.l2c.tagsinuse 36091.013712 # Cycle average of tags in use
+system.l2c.total_refs 866394 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 88928 # number of writebacks
+system.l2c.writebacks 90126 # number of writebacks
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-host_inst_rate 546024 # Simulator instruction rate (inst/s)
-host_mem_usage 378800 # Number of bytes of host memory used
-host_seconds 92.51 # Real time elapsed on the host
-host_tick_rate 1297642212 # Simulator tick rate (ticks/s)
+host_inst_rate 571745 # Simulator instruction rate (inst/s)
+host_mem_usage 384580 # Number of bytes of host memory used
+host_seconds 88.62 # Real time elapsed on the host
+host_tick_rate 1356995451 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 50513922 # Number of instructions simulated
-sim_seconds 0.120048 # Number of seconds simulated
-sim_ticks 120048264000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 99871 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 99871 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14859.416446 # average LoadLockedReq miss latency
+sim_insts 50669854 # Number of instructions simulated
+sim_seconds 0.120262 # Number of seconds simulated
+sim_ticks 120261685000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0 100213 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 100213 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15144.474290 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11859.416446 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12144.474290 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
-system.cpu.dcache.LoadLockedReq_hits::0 94593 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 94593 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 78428000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052848 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 5278 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 5278 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 62594000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052848 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_hits::0 95001 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 95001 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 78933000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.052009 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 5212 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 5212 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 63297000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.052009 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 5278 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310054500 # number of LoadLockedReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_accesses::0 7793356 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 7793356 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15742.239268 # average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses 5212 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_uncacheable_latency 310267000 # number of LoadLockedReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_accesses::0 7824422 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 7824422 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 15793.989050 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12741.872084 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12793.661656 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7557779 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7557779 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3708509500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.030228 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 235577 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 235577 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3001692000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030228 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 7587704 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7587704 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3738721500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.030254 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 236718 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 236718 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency 3028490000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.030254 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 235577 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43427916500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 99870 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 99870 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 99870 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 99870 # number of StoreCondReq hits
-system.cpu.dcache.WriteReq_accesses::0 6647889 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6647889 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 40318.665363 # average WriteReq miss latency
+system.cpu.dcache.ReadReq_mshr_misses 236718 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 43432839000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0 100212 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 100212 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_hits::0 100212 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 100212 # number of StoreCondReq hits
+system.cpu.dcache.WriteReq_accesses::0 6671650 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6671650 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 40817.981450 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37318.368117 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37817.693965 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 6472950 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 6472950 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 7053307000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.026315 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 174939 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 174939 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 6528438000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.026315 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 6499467 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6499467 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7028162500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.025808 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 172183 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 172183 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 6511564000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.025808 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 174939 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 926045500 # number of WriteReq MSHR uncacheable cycles
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system.cpu.itb.misses 2819 # DTB misses
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 240096528 # number of cpu cycles simulated
-system.cpu.num_insts 50513922 # Number of instructions executed
-system.cpu.num_refs 16229722 # Number of memory references
+system.cpu.numCycles 240523370 # number of cpu cycles simulated
+system.cpu.num_insts 50669854 # Number of instructions executed
+system.cpu.num_refs 16289326 # Number of memory references
system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 0 # number of writebacks
system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency inf # average LoadLockedReq mshr uncacheable latency
-system.l2c.LoadLockedReq_mshr_uncacheable_latency 234000000 # number of LoadLockedReq MSHR uncacheable cycles
-system.l2c.ReadExReq_accesses::0 173200 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 173200 # number of ReadExReq accesses(hits+misses)
+system.l2c.LoadLockedReq_mshr_uncacheable_latency 234160000 # number of LoadLockedReq MSHR uncacheable cycles
+system.l2c.ReadExReq_accesses::0 170437 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 170437 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_avg_miss_latency::0 52000 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_hits::0 65260 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 65260 # number of ReadExReq hits
-system.l2c.ReadExReq_miss_latency 5612880000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 0.623210 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 107940 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 107940 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 4317600000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 0.623210 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_hits::0 62185 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 62185 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 5629104000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.635144 # miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_misses::total 108252 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 4330080000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 0.635144 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 107940 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 669099 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 7756 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 676855 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52101.691699 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 26691986.111111 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 26744087.802810 # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses 108252 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0 673342 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 5664 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 679006 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52102.216096 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1 26560864.864865 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 26612967.080961 # average ReadReq miss latency
system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 650656 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 7720 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 658376 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 960911500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.027564 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.004642 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.032206 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 18443 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 36 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 18479 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 739160000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.027618 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.382543 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 2.410160 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 18479 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 33151541000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses::0 1739 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 1739 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 392.794887 # average UpgradeReq miss latency
+system.l2c.ReadReq_hits::0 654480 # number of ReadReq hits
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+system.l2c.ReadReq_hits::total 660107 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 982752000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.028013 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.006532 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.034545 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 18862 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 37 # number of ReadReq misses
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+system.l2c.ReadReq_mshr_miss_latency 755960000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.028067 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 3.336688 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 3.364755 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses 18899 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 33155867000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses::0 1746 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 1746 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 721.804511 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_hits::0 18 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 18 # number of UpgradeReq hits
-system.l2c.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 0.989649 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 1721 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 1721 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 68840000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.989649 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_hits::0 17 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 17 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency 1248000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.990263 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 1729 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 1729 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 69160000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 0.990263 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 1721 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 1729 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_mshr_uncacheable_latency 739844000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 415688 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 415688 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 415688 # number of Writeback hits
-system.l2c.Writeback_hits::total 415688 # number of Writeback hits
+system.l2c.Writeback_accesses::0 416632 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 416632 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 416632 # number of Writeback hits
+system.l2c.Writeback_hits::total 416632 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 6.983802 # Average number of references to valid blocks.
+system.l2c.avg_refs 6.976763 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 842299 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 7756 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 850055 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52014.839812 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 182605319.444444 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 182657334.284257 # average overall miss latency
+system.l2c.demand_accesses::0 843779 # number of demand (read+write) accesses
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+system.l2c.demand_accesses::total 849443 # number of demand (read+write) accesses
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+system.l2c.demand_avg_miss_latency::1 178698810.810811 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 178750825.978298 # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.l2c.demand_hits::0 715916 # number of demand (read+write) hits
-system.l2c.demand_hits::1 7720 # number of demand (read+write) hits
-system.l2c.demand_hits::total 723636 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 6573791500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.150045 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.004642 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.154687 # miss rate for demand accesses
-system.l2c.demand_misses::0 126383 # number of demand (read+write) misses
-system.l2c.demand_misses::1 36 # number of demand (read+write) misses
-system.l2c.demand_misses::total 126419 # number of demand (read+write) misses
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+system.l2c.demand_misses::1 37 # number of demand (read+write) misses
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system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 5056760000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.150088 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 16.299510 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 16.449598 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 126419 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 5086040000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.150692 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 22.448976 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 22.599668 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 127151 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.086001 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.479853 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5636.151787 # Average occupied blocks per context
-system.l2c.occ_blocks::1 31447.614519 # Average occupied blocks per context
-system.l2c.overall_accesses::0 842299 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 7756 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 850055 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52014.839812 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 182605319.444444 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 182657334.284257 # average overall miss latency
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+system.l2c.occ_%::1 0.478511 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 5721.907765 # Average occupied blocks per context
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system.l2c.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 715916 # number of overall hits
-system.l2c.overall_hits::1 7720 # number of overall hits
-system.l2c.overall_hits::total 723636 # number of overall hits
-system.l2c.overall_miss_latency 6573791500 # number of overall miss cycles
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-system.l2c.overall_misses::1 36 # number of overall misses
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+system.l2c.overall_misses::0 127114 # number of overall misses
+system.l2c.overall_misses::1 37 # number of overall misses
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system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 5056760000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.150088 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 16.299510 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 16.449598 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 126419 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 33891385000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency 5086040000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.150692 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 22.448976 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 22.599668 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 127151 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 33895711000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 93485 # number of replacements
-system.l2c.sampled_refs 125077 # Sample count of references to valid blocks.
+system.l2c.replacements 94181 # number of replacements
+system.l2c.sampled_refs 125790 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 37083.766306 # Cycle average of tags in use
-system.l2c.total_refs 873513 # Total number of references to valid blocks.
+system.l2c.tagsinuse 37081.608797 # Cycle average of tags in use
+system.l2c.total_refs 877607 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 87014 # number of writebacks
+system.l2c.writebacks 87612 # number of writebacks
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff