but off of Vectorisation ISAs as well. No more separate Vector
instructions.
+# Major opcodes summary
+
+Please be advised that even though below is entirely DRAFT status, there
+is considerable concern that because there is not yet any two-way
+day-to-day communication established with the OPF ISA WG, we have
+no idea if any of these are conflicting with future plans by any OPF
+Members. **The External ISA WG RFC Process is yet to be ratified
+and Libre-SOC may not join the OPF as an entity because it does
+not exist except in name. Even if it existed it would be a conflict
+of interest to join the OPF, due to our funding remit from NLnet**.
+We therefore proceed on the basis of making public the intention to
+submit RFCs once the External ISA WG RFC Process is in place and,
+in a wholly unsatisfactory manner have to *hope and trust* that
+OPF ISA WG Members are reading this and take it into consideration.
+
+**None of these Draft opcodes are intended for private custom
+secret proprietary usage. They are all intended for entirely
+public, upstream, high-profile mass-volume day-to-day usage at the
+same level as add, popcnt and fld**
+
+* SVP64 requires 25% of EXT01 (bits 6 and 9 set to 1)
+* bitmanip requires two major opcodes (due to 16+ bit immediates)
+ those are currently EXT022 and EXT05.
+* brownfield encoding in one of those two major opcodes still
+ requires multiple VA-Form operations (in greater numbers
+ than EXT04 has spare) currently in EXT022 (which is under
+ severe design pressure)
+* space in EXT019 next to addpcis and crops is recommended
+* many X-Form opcodes currently in EXT022 have no preference
+ for a location at all, and may be moved to EXT059, EXT019,
+ EXT031 or other much more suitable location.
+
+# Sub-pages
+
Pages being developed and examples
* [[sv/overview]] explaining the basics.