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diff --git a/openpower/sv/vector_swizzle.mdwn b/openpower/sv/vector_swizzle.mdwn
index 4b6688a19128044333aaf1646073c80589e9c99d..6eea7a9ad528e2030ecff8b0b120f728dd7d9ca6 100644 (file)
--- a/openpower/sv/vector_swizzle.mdwn
+++ b/openpower/sv/vector_swizzle.mdwn
@@ -1,6 +1,7 @@
 # SV Vector Prefix Swizzle
 
-<https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=139>
+* <https://libre-soc.org/simple_v_extension/specification/mv.x/>
 
 3D GPU operations on batches of vec2, vec3 and vec4 often require re-ordering of the elements in an "out of lane" fashion with respect to standard high performance non-GPU-centric Vector Processors.  Examples include: